-
1
-
-
52649179411
-
Multiprocessor System-on-Chip (MPSoC) Technology
-
oct.
-
W. Wolf et al., "Multiprocessor System-on-Chip (MPSoC) Technology," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 27, no. 10, pp. 1701-1713, oct. 2008.
-
(2008)
IEEE Trans. Computer-Aided Design Integr. Circuits Syst.
, vol.27
, Issue.10
, pp. 1701-1713
-
-
Wolf, W.1
-
2
-
-
70350051158
-
Multi-core for Mobile Phones
-
C. H. K. van Berkel, "Multi-core for Mobile Phones," in in Proc. of DATE '09, pp. 1260-1265.
-
Proc. of DATE '09
, pp. 1260-1265
-
-
Van Berkel, C.H.K.1
-
3
-
-
84939698077
-
Synchronous Data Flow
-
Sept.
-
E. Lee et al., "Synchronous Data Flow," in Proc. of the IEEE, vol. 75, no. 9, pp. 1235-1245, Sept. 1987.
-
(1987)
Proc. of the IEEE
, vol.75
, Issue.9
, pp. 1235-1245
-
-
Lee, E.1
-
4
-
-
0000087207
-
The Semantics of a Simple Language for Parallel Programming
-
J. L. Rosenfeld, Ed.
-
G. Kahn, "The Semantics of a Simple Language for Parallel Programming," in IFIP Congress'74, J. L. Rosenfeld, Ed.
-
IFIP Congress'74
-
-
Kahn, G.1
-
5
-
-
57649168358
-
A Control Theoretic Approach to Energy-efficient Pipelined Computation in MPSoCs
-
September
-
S. Carta et al., "A Control Theoretic Approach to Energy-efficient Pipelined Computation in MPSoCs," ACM Trans. Embed. Comput. Syst., vol. 6, September 2007.
-
(2007)
ACM Trans. Embed. Comput. Syst.
, vol.6
-
-
Carta, S.1
-
6
-
-
80052672706
-
Low-power Adaptive Pipelined MPSoCs for Multimedia: An H.264 Video Encoder Case Study
-
H. Javaid et al., "Low-power Adaptive Pipelined MPSoCs for Multimedia: An H.264 Video Encoder Case Study," in in Proc. of DAC '11, june, pp. 1032-1037.
-
Proc. of DAC '11, June
, pp. 1032-1037
-
-
Javaid, H.1
-
8
-
-
84863550651
-
-
[Online]
-
"Keystone Device Architecture,"Texas Instruments. [Online]: http://processors.wiki.ti.com/index.php/Keystone
-
Keystone Device Architecture
-
-
-
9
-
-
77951218955
-
MPSoC Programming using the MAPS Compiler
-
R. Leupers et al., "MPSoC Programming using the MAPS Compiler," in in Proc. ASP-DAC'10, pp. 897-902.
-
Proc. ASP-DAC'10
, pp. 897-902
-
-
Leupers, R.1
-
10
-
-
84876232608
-
MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs
-
Oct
-
J. Castrillon et al., "MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs," IEEE Trans Ind. Informat., vol. PP, no. 99, p. 19, Oct 2011.
-
(2011)
IEEE Trans Ind. Informat.
, vol.PP
, Issue.99
, pp. 19
-
-
Castrillon, J.1
-
11
-
-
84863558064
-
Automatic Partitioning and Mapping of Stream-based Applications onto the Intel IXP Network Processor
-
ACM
-
S. Meijer et al., "Automatic Partitioning and Mapping of Stream-based Applications onto the Intel IXP Network Processor," in in Proc. the SCOPES'07. ACM, pp. 23-30.
-
Proc. the SCOPES'07
, pp. 23-30
-
-
Meijer, S.1
-
12
-
-
70350380177
-
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell
-
D. Nadezhkin et al., "Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell," in in Proc. of SAMOS'09, pp. 308-317.
-
Proc. of SAMOS'09
, pp. 308-317
-
-
Nadezhkin, D.1
-
13
-
-
0003570574
-
-
Ph.D. dissertation, EECS Department, UCB, CA, USA
-
T. M. Parks, "Bounded scheduling of process networks," Ph.D. dissertation, EECS Department, UCB, CA, USA, 1995.
-
(1995)
Bounded Scheduling of Process Networks
-
-
Parks, T.M.1
-
14
-
-
35248815492
-
Requirements on the Execution of Kahn Process Networks
-
Springer Verlag
-
M. Geilen et al., "Requirements on the Execution of Kahn Process Networks," in in Proc. of ESOP'03. Springer Verlag, pp. 319-334.
-
Proc. of ESOP'03
, pp. 319-334
-
-
Geilen, M.1
-
16
-
-
0002050141
-
Static scheduling algorithms for allocating directed task graphs to multiprocessors
-
Y.-K. Kwok et al., "Static scheduling algorithms for allocating directed task graphs to multiprocessors," ACM Comput. Surv., vol. 31, no. 4, pp. 406-471, 1999.
-
(1999)
ACM Comput. Surv.
, vol.31
, Issue.4
, pp. 406-471
-
-
Kwok, Y.-K.1
-
17
-
-
47949128964
-
Automatic Buffer Sizing for Rate-constrained KPN Applications on Multiprocessor System-on-Chip
-
IEEE Computer Society
-
E. Cheung et al., "Automatic Buffer Sizing for Rate-constrained KPN Applications on Multiprocessor System-on-Chip," in in Proc. IEEE Int. High Level Design Validation Workshop. IEEE Computer Society, 2007, pp. 37-44.
-
(2007)
Proc. IEEE Int. High Level Design Validation Workshop
, pp. 37-44
-
-
Cheung, E.1
-
18
-
-
34547357400
-
Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs
-
ACM
-
S. Stuijk et al., "Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs," in in Proc. DAC '07. ACM, pp. 777-782.
-
Proc. DAC '07
, pp. 777-782
-
-
Stuijk, S.1
-
20
-
-
77953089980
-
Throughput modeling to evaluate process merging transformations in polyhedral process networks
-
S. Meijer et al., ""throughput modeling to evaluate process merging transformations in polyhedral process networks"," in in Proc. DATE'10, pp. 747-752.
-
Proc. DATE'10
, pp. 747-752
-
-
Meijer, S.1
-
21
-
-
33744752126
-
Multiobjective Optimization and Evolutionary Algorithms for the Application Mapping Problem in Multiprocessor System-on-Chip Design
-
june
-
C. Erbas et al., "Multiobjective Optimization and Evolutionary Algorithms for the Application Mapping Problem in Multiprocessor System-on-Chip Design," IEEE Trans. Evol. Comput., vol. 10, no. 3, pp. 358-374, june 2006.
-
(2006)
IEEE Trans. Evol. Comput.
, vol.10
, Issue.3
, pp. 358-374
-
-
Erbas, C.1
-
22
-
-
51149120769
-
Mapping Applications to Tiled Multiprocessor Embedded Systems
-
Washington, DC, USA: IEEE Computer Society
-
L. Thiele et al., "Mapping Applications to Tiled Multiprocessor Embedded Systems," in in Proc. of ACSD '07. Washington, DC, USA: IEEE Computer Society, pp. 29-40.
-
Proc. of ACSD '07
, pp. 29-40
-
-
Thiele, L.1
-
23
-
-
0027542932
-
A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures
-
G. C. Sih et al., "A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures," IEEE Trans. Parallel Distrib. Syst., vol. 4, no. 2, pp. 175-187, 1993.
-
(1993)
IEEE Trans. Parallel Distrib. Syst.
, vol.4
, Issue.2
, pp. 175-187
-
-
Sih, G.C.1
-
24
-
-
84872957652
-
-
[Online]
-
Synopsys, "Processor Designer." [Online]: http://www.synopsys. com/Tools/SLD/ProcessorDev/Pages/default.aspx
-
Processor Designer
-
-
-
25
-
-
84864944578
-
-
[Online]
-
-, "Platform Architect." [Online]: http://www.synopsys.com/ Tools/SLD/VirtualPrototyping/Pages/PlatformArchitect.aspx
-
Platform Architect
-
-
-
26
-
-
45149132825
-
SDF3: SDF for Free
-
IEEE Comp. Soc., June
-
S. Stuijk et al., "SDF3: SDF For Free," in in Proc. of ACSD'06. IEEE Comp. Soc., June, pp. 276-278.
-
Proc. of ACSD'06
, pp. 276-278
-
-
Stuijk, S.1
|