Reducing OLTP instruction misses with thread migration

8th International Workshop on Data Management on New Hardware, DaMoN 2012 - In Conjunction with ACM SIGMOD/PODS Conference

Volumn , Issue , 2012, Pages 9-15

  Atta, Islam ^b   Tözün, Pinar ^a   Ailamaki, Anastasia ^a   Moshovos, Andreas ^b  

^a EPFL   (Switzerland)

^b UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE CAPACITY; CODE INSTRUMENTATION; MANY-CORE; MISS-RATE; MODERN PROCESSORS; ONLINE TRANSACTION PROCESSING; POTENTIAL SOLUTIONS; THREAD MIGRATION;

CACHE MEMORY; INFORMATION MANAGEMENT;

HARDWARE;

EID: 84863500160     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2236584.2236586     Document Type: Conference Paper

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