Multi-step ART1 algorithm for recognition of defect patterns on semiconductor wafers

International Journal of Production Research

Volumn 50, Issue 12, 2012, Pages 3274-3287

  Choi, Gyunghyun ^a   Kim, Sung Hee ^a   Ha, Chunghun ^b   Bae, Suk Joo ^a  

^a Hanyang University   (South Korea)

^b Hong Ik University   (South Korea)

Author keywords

neural network; pattern recognition; similarity; spatial defects; wafer map; yield management

Indexed keywords

ADAPTIVE RESONANCE THEORY; COMPUTATIONAL TESTING; DEFECT PATTERNS; GENERATING MECHANISM; HOMOGENEOUS POISSON PROCESS; IC DEFECTS; MULTI-STEP; MULTIVARIATE NORMAL; ON-WAFER; PRE-PROCESSING; PRINCIPAL CURVE; RANDOM PATTERN; RING PATTERNS; RUN-LENGTH ENCODING; SEMI-CONDUCTOR WAFER; SEMICONDUCTOR MANUFACTURING PROCESS; SIMILARITY; SIMILARITY MEASURE; SPATIAL PATTERNS; SPHERICAL SHELL; STATISTICAL MODELS; VARIABLE RESOLUTION; WAFER MAPS; YIELD MANAGEMENT; INTEGRATED CIRCUITS (ICS);

ALGORITHMS; COMPUTER SIMULATION; DEFECTS; NEURAL NETWORKS; PATTERN RECOGNITION; POISSON DISTRIBUTION; SEMICONDUCTOR DEVICE MANUFACTURE; COMPUTATION THEORY; INTEGRATED CIRCUITS; SILICON WAFERS;

SILICON WAFERS; PATTERN RECOGNITION;

EID: 84863209634     PISSN: 00207543     EISSN: 1366588X     Source Type: Journal    
DOI: 10.1080/00207543.2011.574502     Document Type: Article

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