A neural-network approach for semiconductor wafer post-sawing inspection

IEEE Transactions on Semiconductor Manufacturing

Volumn 15, Issue 2, 2002, Pages 260-266

  Su, Chao Ton ^a   Yang, Taho ^b   Ke, Chir Mour ^c  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^c Lightsonic Optoelectronics Inc   (Taiwan)

Author keywords

Defect; Neural network; Post sawing inspection; Semiconductor wafer

Indexed keywords

BACKPROPAGATION; DEFECTS; INTEGRATED CIRCUIT LAYOUT; SCANNING ELECTRON MICROSCOPY;

SEMICONDUCTOR WAFERS;

NEURAL NETWORKS;

EID: 0036565004     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.999602     Document Type: Conference Paper

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