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Volumn 6, Issue 3, 2012, Pages 153-159

Machine learning predictive modelling high-level synthesis design space exploration

Author keywords

[No Author keywords available]

Indexed keywords

ERROR THRESHOLD; HIGH LEVEL SYNTHESIS; PREDICTIVE MODELLING; PREDICTIVE MODELS; RUNTIMES; TRAINING SETS;

EID: 84863186174     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2011.0115     Document Type: Article
Times cited : (56)

References (18)
  • 1
    • 0027963994 scopus 로고
    • Design-space exploration for high-level synthesis
    • Ahmad, I., Dhodi, M., and Hielscher, F.: 'Design-space exploration for high-level synthesis', Comput. Commun., 1994, p. 491-496
    • (1994) Comput. Commun. , pp. 491-496
    • Ahmad, I.1    Dhodi, M.2    Hielscher, F.3
  • 2
    • 46749154326 scopus 로고    scopus 로고
    • Design space exploration with evolutionary multi-objective optimisation
    • Holzer, M., Knerr, B., and Rupp, M.: 'Design space exploration with evolutionary multi-objective optimisation', Proc. Ind. Embedded Syst., 2007, p. 125-133
    • (2007) Proc. Ind. Embedded Syst. , pp. 125-133
    • Holzer, M.1    Knerr, B.2    Rupp, M.3
  • 4
    • 11244278278 scopus 로고    scopus 로고
    • CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems
    • Haubelt, C., and Teich, J.: 'CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems', ASAP, 2004, p. 28-40
    • (2004) ASAP , pp. 28-40
    • Haubelt, C.1    Teich, J.2
  • 5
    • 58049100177 scopus 로고    scopus 로고
    • SC build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gates arrays
    • 10.1049/iet-cdt:20070120
    • Anderson, I.D.L., and SKhalid, M.A.: 'SC build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gates arrays', IET Comput. Digit. Tech., 2009, p. 24-3210.1049/iet-cdt:20070120
    • (2009) IET Comput. Digit. Tech. , pp. 24-32
    • Anderson, I.D.L.1    SKhalid, M.A.2
  • 6
    • 0036036127 scopus 로고    scopus 로고
    • A Compiler approach to fast hardware design space exploration in FPGA-based systems
    • So, B., Hall, M.W., and Diniz, P.C.: 'A Compiler approach to fast hardware design space exploration in FPGA-based systems', IET Comput. Digit. Tech., 2002, p. 165-176
    • (2002) IET Comput. Digit. Tech. , pp. 165-176
    • So, B.1    Hall, M.W.2    Diniz, P.C.3
  • 7
    • 0042635700 scopus 로고    scopus 로고
    • Using estimates from behavioral synthesis tools in compiler-directed design space exploration
    • So, B., Diniz, P.C., and Hall, M.W.: 'Using estimates from behavioral synthesis tools in compiler-directed design space exploration', DAC, 2003, p. 512-519
    • (2003) DAC , pp. 512-519
    • So, B.1    Diniz, P.C.2    Hall, M.W.3
  • 8
    • 0036705159 scopus 로고    scopus 로고
    • System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
    • 10.1109/TVLSI.2002.807764, 1063-8210
    • Givargis, T., Vahid, F., and Henkel, J.: 'System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip', IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2002, 10, (4), p. 416-42210.1109/TVLSI.2002.807764 1063-8210
    • (2002) IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol.10 , Issue.4 , pp. 416-422
    • Givargis, T.1    Vahid, F.2    Henkel, J.3
  • 9
    • 84863225681 scopus 로고    scopus 로고
    • Adaptive simulated annealer for high level synthesis design space exploration
    • Carrion Schafer, B., Takenaka, T., and Wakabayashi, K.: 'Adaptive simulated annealer for high level synthesis design space exploration', VLSI DAT, 2009, p. 509-519
    • (2009) VLSI DAT , pp. 509-519
    • Carrion Schafer, B.1    Takenaka, T.2    Wakabayashi, K.3
  • 11
    • 34248506586 scopus 로고    scopus 로고
    • Efficient design space exploration for application specific systems-on-a-chip
    • 10.1016/j.sysarc.2007.01.004, 1383-7621
    • Ascia, G., Catania, V., Di Nuovo, A.G., Palesi, M., and Patti, D.: 'Efficient design space exploration for application specific systems-on-a-chip', J. Syst. Archit., 2007, 53, p. 733-75010.1016/j.sysarc.2007.01.004 1383-7621
    • (2007) J. Syst. Archit. , vol.53 , pp. 733-750
    • Ascia, G.1    Catania, V.2    Di Nuovo, A.G.3    Palesi, M.4    Patti, D.5
  • 13
    • 0004204162 scopus 로고    scopus 로고
    • Data mining
    • Morgan Kaufmann,ISBN-13:978-0-12-0808407-0
    • Witten, I.H., and Frank, E.: 'Data mining', (Morgan Kaufmann 2005), ISBN-13:978-0-12-0808407-0
    • (2005)
    • Witten, I.H.1    Frank, E.2
  • 14
    • 4444356709 scopus 로고    scopus 로고
    • A GA based design space exploration framework for parameterized system-on-a-chip platforms
    • 10.1109/TEVC.2004.826389, 1089-778X
    • Ascia, A., Catania, V., and Palesi, M.: 'A GA based design space exploration framework for parameterized system-on-a-chip platforms', IEEE Trans. Evol. Comput., 2004, 8, (4), p. 329-34610.1109/TEVC.2004.826389 1089-778X
    • (2004) IEEE Trans. Evol. Comput. , vol.8 , Issue.4 , pp. 329-346
    • Ascia, A.1    Catania, V.2    Palesi, M.3
  • 15
    • 84947926042 scopus 로고    scopus 로고
    • A fast elitist non-dominated sorting genetic algorithm for multi-objective optimization: Nsga-ii
    • Kalyanmoy, D., Agrawal, S., Pratap, A., and Meyarivan, T.: 'A fast elitist non-dominated sorting genetic algorithm for multi-objective optimization: Nsga-ii', Parallel Prob. Solving Nat., 2000, p. 849-858
    • (2000) Parallel Prob. Solving Nat. , pp. 849-858
    • Kalyanmoy, D.1    Agrawal, S.2    Pratap, A.3    Meyarivan, T.4
  • 16
    • 0033676661 scopus 로고    scopus 로고
    • On measuring multiobjective evolutionary algorithm performance
    • David, A., Veldhuizen, V., and Lamont, B.G.: 'On measuring multiobjective evolutionary algorithm performance', Cong. Evol. Comput., 2000, 1, p. 204-211
    • (2000) Cong. Evol. Comput. , vol.1 , pp. 204-211
    • David, A.1    Veldhuizen, V.2    Lamont, B.G.3
  • 17
    • 0037936618 scopus 로고    scopus 로고
    • Performance assessment of multiobjective optimizers: an analysis and review
    • 10.1109/TEVC.2003.810758, 1089-778X
    • Zitzler, E., Thiele, L., Laumanns, M., Fonseca, C., and da Fonseca, V.G.: 'Performance assessment of multiobjective optimizers: an analysis and review', IEEE Trans. Evol. Comput., 2003, 7, p. 117-13210.1109/TEVC.2003.810758 1089-778X
    • (2003) IEEE Trans. Evol. Comput. , vol.7 , pp. 117-132
    • Zitzler, E.1    Thiele, L.2    Laumanns, M.3    Fonseca, C.4    da Fonseca, V.G.5
  • 18
    • 84863225684 scopus 로고    scopus 로고
    • www.cyberworkbench.com


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.