A GA-based design space exploration framework for parameterized system-on-a-chip platforms

IEEE Transactions on Evolutionary Computation

Volumn 8, Issue 4, 2004, Pages 329-346

  Ascia, Giuseppe ^a   Catania, Vincenzo ^a   Palesi, Maurizio ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN SPACE EXPLORATION; MULTIOBJECTIVE OPTIMIZATION; PARAMETERIZED SYSTEMS; PARETO OPTIMAL CONFIGURATIONS; SYSTEM-ON-A-CHIP ARCHITECTURES;

COMPUTER SIMULATION; CONSTRAINT THEORY; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; PARETO PRINCIPLE; REDUCED INSTRUCTION SET COMPUTING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

GENETIC ALGORITHMS;

EID: 4444356709     PISSN: 1089778X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEVC.2004.826389     Document Type: Article

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