-
1
-
-
73249115086
-
Adaptive simulated annealer for high-level synthesis design space exploration
-
B. C. Schafer, T. Takenaka, and K. Wakabayashi, "Adaptive simulated annealer for high-level synthesis design space exploration," in Proc. Int. Symp. Very-Large-Scale Integration Design, Automat., Test, 2009, pp. 106-109.
-
(2009)
Proc. Int. Symp. Very-Large-Scale Integration Design, Automat., Test
, pp. 106-109
-
-
Schafer, B.C.1
Takenaka, T.2
Wakabayashi, K.3
-
3
-
-
73249118881
-
-
[Online]. Available
-
Single Assignment C (SA-C) [Online]. Available: http://www.cs..colostate. edu/cameron
-
Single Assignment C (SA-C)
-
-
-
4
-
-
51549093427
-
SystemCo-designer: Automatic design space exploration and rapid prototyping from behavioral models
-
C. Haubelt, T. Schlichter, J. Keinert, and M. Meredith, "SystemCo- Designer: Automatic design space exploration and rapid prototyping from behavioral models," in Proc. Design Automat. Conf., 2008, pp. 580-585.
-
(2008)
Proc. Design Automat. Conf.
, pp. 580-585
-
-
Haubelt, C.1
Schlichter, T.2
Keinert, J.3
Meredith, M.4
-
5
-
-
34547173196
-
Design space exploration of real-time multimedia MPSoCs with heterogeneous scheduling policies
-
M. Kim, S. Banerjee, N. Dutt, and N. Venkatasubramanian, "Design space exploration of real-time multimedia MPSoCs with heterogeneous scheduling policies," in Proc. Int. Conf. Hardware/Software Codesign Syst. Synthesis (CODES+ISSS), 2006, p. 1621.
-
(2006)
Proc. Int. Conf. Hardware/Software Codesign Syst. Synthesis (CODES+ISSS)
, pp. 1621
-
-
Kim, M.1
Banerjee, S.2
Dutt, N.3
Venkatasubramanian, N.4
-
6
-
-
34047173119
-
Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems
-
S. Mamagkakis, D. Atienza, C. Poucet, F. Catthoor, D. Soudris, and J. M. Mendias, "Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems," in Proc. Design, Automat., Test Eur., 2006, pp. 874-875.
-
(2006)
Proc. Design, Automat., Test Eur.
, pp. 874-875
-
-
Mamagkakis, S.1
Atienza, D.2
Poucet, C.3
Catthoor, F.4
Soudris, D.5
Mendias, J.M.6
-
7
-
-
0027963994
-
Design-Space exploration for high-level synthesis
-
I. Ahmad, M. Dhodi, and F. Hielscher, "Design-Space exploration for high-level synthesis," in Proc. IEEE 13th Ann. Int. Phoenix Conf. Comput. Commun., 1994, pp. 491-496.
-
(1994)
Proc. IEEE 13th Ann. Int. Phoenix Conf. Comput. Commun.
, pp. 491-496
-
-
Ahmad, I.1
Dhodi, M.2
Hielscher, F.3
-
8
-
-
46749154326
-
Design space exploration with evolutionary multiobjective optimization
-
M. Holzer, B. Knerr, and M. Rupp, "Design space exploration with evolutionary multiobjective optimization," in Proc. Ind. Embedded Syst., 2007, pp. 125-133.
-
(2007)
Proc. Ind. Embedded Syst.
, pp. 125-133
-
-
Holzer, M.1
Knerr, B.2
Rupp, M.3
-
10
-
-
11244278278
-
CHARMED: A multiobjective cosynthesis framework for multimode embedded systems
-
V. Kianzad and S. S. Bhattacharyya, "CHARMED: A multiobjective cosynthesis framework for multimode embedded systems," in Proc. IEEE Int. Conf. Applicat.-Specific Syst., Architect., Processors, 2004, pp. 28-40.
-
(2004)
Proc. IEEE Int. Conf. Applicat.-Specific Syst., Architect., Processors
, pp. 28-40
-
-
Kianzad, V.1
Bhattacharyya, S.S.2
-
11
-
-
33748323315
-
Design space pruning through early estimation of area/delay trade-offs for FPGA implementations
-
Oct
-
S. Bilavarn, G. Gogniat, J.-L. Philippe, and L. Bossuet, "Design space pruning through early estimation of area/delay trade-offs for FPGA implementations," in Proc. Int. Conf. Comput. Aided Design, vol.25. Oct. 2006, pp. 1950-1968.
-
(2006)
Proc. Int. Conf. Comput. Aided Design
, vol.25
, pp. 1950-1968
-
-
Bilavarn, S.1
Gogniat, G.2
Philippe, J.-L.3
Bossuet, L.4
-
12
-
-
58049100177
-
SC Build: A computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gates arrays
-
Jan
-
I. D. L. Anderson and M. A. S. Khalid, "SC Build: A computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gates arrays," Inst. Eng. Technol. Comput. Digital Tech., vol.3, no.1, pp. 24-32, Jan. 2009.
-
(2009)
Inst. Eng. Technol. Comput. Digital Tech.
, vol.3
, Issue.1
, pp. 24-32
-
-
Anderson, I.D.L.1
Khalid, M.A.S.2
-
13
-
-
0036036127
-
A compiler approach to fast hardware design space exploration in FPGA-based systems
-
Jun
-
B. So, M. W. Hall, and P. C. Diniz, "A compiler approach to fast hardware design space exploration in FPGA-based systems," in Proc. Conf. Program. Language Design Implement., Jun. 2002, pp. 165-176.
-
(2002)
Proc. Conf. Program. Language Design Implement
, pp. 165-176
-
-
So, B.1
Hall, M.W.2
Diniz, P.C.3
-
14
-
-
0042635700
-
Using estimates from behavioral synthesis tools in compiler-directed design space exploration
-
B. So, P. C. Diniz, and M. W. Hall, "Using estimates from behavioral synthesis tools in compiler-directed design space exploration," in Proc. Design Automat. Conf., 2003, pp. 514-519.
-
(2003)
Proc. Design Automat. Conf.
, pp. 514-519
-
-
So, B.1
Diniz, P.C.2
Hall, M.W.3
-
15
-
-
73249146636
-
All-in-C behavioral synthesis and verification with cyberworkbench
-
Berlin, Germany: Springer-Verlag, ch. 7
-
P. Coussy and A. Moraweic, "All-in-C behavioral synthesis and verification with CyberWorkBench" in High-Level Synthesis from Algorithm Digital Circuit. Berlin, Germany: Springer-Verlag, 2008, ch. 7, pp. 113-127.
-
(2008)
High-Level Synthesis from Algorithm Digital Circuit
, pp. 113-127
-
-
Coussy, P.1
Moraweic, A.2
|