Chemical-mechanical polishing aware application-specific 3D NoC design

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2011, Pages 207-212

  Jang, Wooyoung ^a   He, Ou ^a,b   Yang, Jae Seok ^a   Pan, David Z ^a,c  

^a SAMSUNG Electronics   (South Korea)

^b IBM Research   (China)

^c The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADJACENT LAYERS; BONDING FAILURE; FLOORPLANS; HEIGHT VARIATION; LOWER-POWER CONSUMPTION; METAL DENSITY; NETWORK-ON-CHIP DESIGN; NOC DESIGN; ROUTING PATH; SILICON LAYER; THREE-DIMENSIONAL (3D); THROUGH-SILICON-VIA;

CHEMICAL MECHANICAL POLISHING; COMPUTER AIDED DESIGN; POLISHING; THREE DIMENSIONAL; TOPOLOGY; VLSI CIRCUITS;

ROUTERS;

EID: 84862951004     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105327     Document Type: Conference Paper

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