A 60 GHz current-reuse LO-boosting mixer in 90 nm CMOS

IEEE Microwave and Wireless Components Letters

Volumn 22, Issue 3, 2012, Pages 135-137

  Byeon, Chul Woo ^a   Lee, Jae Jin ^a   Song, In Sang ^a   Park, Chul Soon ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

60 GHz; CMOS; current reuse; LO boosting; mixer

Indexed keywords

60 GHZ; 60 GHZ BAND; CMOS; CMOS MIXER; CONVERSION GAIN; CURRENT REUSE; DIRECT DOWN CONVERSION MIXERS; INPUT POWER; LO-BOOSTING; LOW-POWER CONSUMPTION; SWITCHING STAGE; TRANSCONDUCTANCE STAGE;

BUFFER AMPLIFIERS; MIXING;

MIXERS (MACHINERY);

EID: 84862793292     PISSN: 15311309     EISSN: None     Source Type: Journal    
DOI: 10.1109/LMWC.2011.2182636     Document Type: Article

References (14)

1. B. Afshar, Y. Wang, and A. M. Niknejad, "A robust 24 mW 60 GHz receiver in 90 nm standard CMOS," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 182-605.
2. T. Mitomo, R. Fujimoto, N. Ono, R. Tachibana, H. Hoshino, Y. Yoshihara, Y. Tsutsumi, and I. Seto, "A 60-GHz CMOS receiver front-end with frequency synthesizer," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1030-1037, Apr. 2008.
3. M. Varonen, M. Karkkainen, M. Kantanen, and K. Halonen, "Millimeter- wave integrated circuits in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 1991-2002, Sep. 2008.
4. D. Y. Jung, J. J. Lee, and C. S. Park, "Low-power and low NF V-band down-converter in 0.13 μ CMOS," IET Electron. Lett., vol. 45, no. 10, pp. 509-510, Mar. 2009.
5. L. Li, P. Reynaert, and M. S. J. Steyaert, "A 60-GHzCMOSVCO using capacitance-splitting and gate-drain impedance-balancing techniques," IEEE Trans. Microw. Theory Tech., vol. 59, no. 2, pp. 406-413, Feb. 2011.
6. J. L. González, F. Badets, B. Martineau, and D. Belot, "A 56-GHz LC-tank VCO with 17% tuning range in 65 nm bulk CMOS for wireless HDMI," IEEE Trans. Microw. Theory Tech., vol. 58, no. 5, pp. 1359-1366, May 2010.
7. K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, "A 57-to-66 GHz quadrature PLL in 45 nm digital CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 494-495, 495a.
8. F. Barale, P. Sen, S. Sarkar, S. Pinel, and J. Laskar, "A 60 GHz-standard compatible programmable 50 GHz phase-locked loop in 90 nm CMOS," IEEE Microw. Wireless Compon. Lett., vol. 20, no. 7, pp. 411-413, Jul. 2010.
9. B. Razavi, "Design of millimeter-wave CMOS radios: A tutorial," IEEE Trans. Circuits Syst. I, vol. 56, no. 1, pp. 4-16, Jan. 2009.
10. K. Raczkowski, S. Thijs, W. De Raedt, B. Nauwelaers, and P. Wambacq, "50-to-67 GHz ESD-protected power amplifiers in digital 45 nm LP CMOS," in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 382-383, 383a.
11. A. M. Mangan, S. P. Voinigescu, M. T. Yang, and M. Tazlauanu, "Deembedding transmission line measurements for accurate modeling of IC designs," IEEE Trans. Electron. Dev., vol. 53, no. 2, pp. 235-241, Feb. 2006.
12. [Online]. Available: http://www.ieee802.org/15/pub/TG3c.html
13. C.-Y. Wang and J.-H. Tsai, "A 51 to 65 GHz low-power bulk-driven mixer using 0.13 μ CMOS technology," IEEE Microw. Wireless Compon. Lett., vol. 19, no. 8, pp. 521-523, Aug. 2009.
14. F. R. Shahroury and C.-Y. Wu, "The design of low LO power 60-GHz CMOSquadrature-balanced self-switching current-mode mixer," IEEE Microw. Wireless Compon. Lett., vol. 18, no. 10, pp. 692-694, Oct. 2008.