Scalable tree-based architectures for IPv4/v6 lookup using prefix partitioning

IEEE Transactions on Computers

Volumn 61, Issue 7, 2012, Pages 1026-1039

  Le, Hoang ^a   Prasanna, Viktor K ^a  

^a University of Southern California ^*  (United States)

Author keywords

field programmable gate array (FPGA); IP Lookup; longest prefix matching; partitioning; pipeline; reconfigurable

Indexed keywords

ADDRESS SPACE; DISJOINT PREFIX; DISTRIBUTED ROUTING; FPGA DEVICES; HIGH THROUGHPUT; INCREMENTAL UPDATES; INTERNET PROTOCOL LOOKUPS; IP LOOKUP; LONGEST-PREFIX MATCHING; LOOKUPS; MEMORY EFFICIENCY; MEMORY FOOTPRINT; MEMORY REQUIREMENTS; ON CHIP MEMORY; PARTITIONING; PIPELINED ARCHITECTURE; PREFIX PARTITIONING; PREFIX PARTITIONING ALGORITHM; PROPOSED ARCHITECTURES; RECONFIGURABLE; RESEARCH COMMUNITIES; ROUTING TABLE; STATE OF THE ART; SUBSTANTIAL REDUCTION; TREE-BASED; TREE-BASED APPROACH;

ALGORITHMS; DATA STRUCTURES; FORESTRY; MEMORY ARCHITECTURE; PIPELINES; RECONFIGURABLE HARDWARE; STATIC RANDOM ACCESS STORAGE; TELECOMMUNICATION NETWORKS;

INTERNET PROTOCOLS;

ALGORITHMS; DATA PROCESSING; DATA STORAGE; HARD WARE; INTERNET; NETWORKS; PIPE LINES; RANDOM PROCESSES; TELECOMMUNICATIONS;

EID: 84861793167     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2011.130     Document Type: Article

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