Scalable high throughput and power efficient IP-lookup on FPGA

Proceedings - IEEE Symposium on Field Programmable Custom Computing Machines, FCCM 2009

Volumn , Issue , 2009, Pages 167-174

  Le, Hoang ^a   Prasanna, Viktor K ^a  

^a University of Southern California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ART DESIGN; HIGH SPEED INTERNET; HIGH THROUGHPUT; I/O PINS; IP LOOKUP; LINEAR PIPELINE; LOOKUPS; LOW-POWER SRAM; MEMORY ACCESS; NON-BLOCKING; ON CHIP MEMORY; ORDER OF MAGNITUDE; POWER DISSIPATION; POWER EFFICIENT; POWER SAVINGS; PROPOSED ARCHITECTURES; ROUTE UPDATES; ROUTING TABLE; TREE TRAVERSAL;

COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERNET PROTOCOLS; LOGIC GATES; ROUTERS; STATIC RANDOM ACCESS STORAGE; TELECOMMUNICATION NETWORKS; THROUGHPUT;

NETWORK ARCHITECTURE;

EID: 74349111608     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2009.42     Document Type: Conference Paper

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