Test generation for multiple-threshold gate-delay fault model

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 244-249

  Nakao, Michinobu ^a   Kiyoshige, Yoshikazu ^a   Hatayama, Kazumi ^a   Sato, Yasuo ^a   Nagumo, Takaharu ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; DELAY CIRCUITS; ELECTRIC FAULT CURRENTS; LSI CIRCUITS; ROBUSTNESS (CONTROL SYSTEMS);

FAULT SIMULATION; MULTIPLE-THRESHOLD GATE-DELAY FAULT MODEL; PATH SELECTION; PATTERN-INDEPENDENT TIMING; TEST GENERATION; TWO-PATTERN TESTS;

INTEGRATED CIRCUIT TESTING;

EID: 0035704288     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

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10. A BIST approach for very deep sub-micron (VDSM) defects
11. Scan-based transition test
12. Broad-side delay test
13. A delay test generator for logic LSI