A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 224-225

  Zhou, Dajiang ^a   Zhou, Jinjia ^a   Zhu, Jiayi ^b   Liu, Peilin ^b   Goto, Satoshi ^a  

^a WASEDA UNIVERSITY   (Japan)

^b SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH REQUIREMENT; CAMERA VIEW; DATA DEPENDENCIES; DIGITAL TV; EMERGING APPLICATIONS; H.264 DECODING; H.264/AVC; HIGH-THROUGHPUT; MACRO BLOCK; SCALABLE ARCHITECTURES; SINGLE-CHIP DESIGNS; SUPER HI-VISION; VIDEO CODING ALGORITHM; VIDEO DECODERS;

DESIGN; MOTION PICTURE EXPERTS GROUP STANDARDS;

DIGITAL TELEVISION;

EID: 84860691324     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176985     Document Type: Conference Paper

References (5)

1. D. Zhou, et al., "A 530 Mpixels/s 4096x2160@60fps H.264/AVC high profile video decoder chip," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 777-788, 2011.
2. T.-D. Chuang, et al., "A 59.5mW scalable/multi-view video decoder chip for quad/3D full HDTV and video streaming applications," ISSCC Dig. Tech. Papers, pp. 330-331, 2010.
3. D. Zhou, et al., "A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective," IEEE Symp. VLSI Circuits, pp. 262-263, 2009.
4. C. Lin, et al., "A 160kgate 4.5kB SRAM H.264 video decoder for HDTV applications,"ISSCC Dig. Tech. Papers, pp. 1596-1605, 2006.
5. http://download.micron.com/downloads/misc/ddr2-power-calc-web.xls