A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 502-503

  Lee, Hyun Woo ^a,b   Kim, Ki Han ^a   Choi, Young Kyoung ^a   Shon, Ju Hwan ^a   Park, Nak Kyu ^a   Kim, Kwan Weon ^a   Kim, Chulwoo ^b   Choi, Young Jung ^a   Chung, Byong Tae ^a  

^a Hynix Semiconductor Inc   (South Korea)

^b Korea University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

CMOS TECHNOLOGY; CONSUMER DRAMS; DYNAMIC VOLTAGE; MOBILE APPLICATIONS; OPERATING FREQUENCY; POWER SUPPLY VOLTAGE; PROCESS TECHNOLOGIES; PROCESS VARIATION;

VOLTAGE SCALING;

EID: 79955733264     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746416     Document Type: Conference Paper

References (4)

1. Dighe. S, et al., "Within-die variation-aware dynamic-voltage- frequency scaling core mapping and thread hopping for an 80-core processor" ISSCC Dig. Tech. Papers, pp. 174-175, Feb. 2010.
2. H. W. Lee, et al., "An 1.6V 3.3Gbps Dual-Mode Phase and Delay Locked Loop using power noise management technique with unregulated power supply for pseudo-rank DRAM in 54nm CMOS technology" ISSCC Dig. Tech. Papers, pp. 140-141, Feb. 2009.
3. W. J. Yun, et al., "A 0.1-to-1.5GHz 4.2mW ALL-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 282-283, Feb. 2008.
4. D. U. Lee, et al., "A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL," ISSCC Dig. Tech. Papers, pp. 547-556, Feb. 2006.