A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 186-187

  Wordeman, Matt ^a   Silberman, Joel ^a   Maier, Gary ^b   Scheuermann, Michael ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D SYSTEMS; CMOS TECHNOLOGY; DESIGN AND OPERATIONS; INTEGRATED SYSTEMS; INTERCONNECT BANDWIDTH; LOGIC BLOCKS; MEMORY LAYERS; POTENTIAL APPLICATIONS; THROUGH SILICON VIAS;

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; PROXY CACHES;

THREE DIMENSIONAL;

EID: 84860654078     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176968     Document Type: Conference Paper

References (6)

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3. J. Barth, et al., "A 45nm SOI Embedded DRAM Macro for Power7™ 32MB On-Chip L2 Cache," ISSCC Dig Tech. Papers, pp. 342-343, 2010.
4. D.F. Wendel, et al., "POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processorm" IEEE J. Solid-State Circuits, vol.46, no. 1, pp. 145-159 2011.
5. M. Farooq, et al., "3D Copper TSV Integration, Testing and Reliability," IEDM Dig. Tech Papers, 2011.
6. J. Golz, et al., "3D Stackable 32nm High-K/Metal gate SOI Embedded DRAM Prototype," IEEE Symp. VLSI Circuits, pp. 228-229, 2011.