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Volumn 46, Issue 1, 2011, Pages 145-161

POWER7™, a highly parallel, scalable multi-core high end server processor

Author keywords

clock grid; Clocked storage element design; CML circuits; debug features; deep trench capacitor; design for reliability; design for test; differential I O; digital PLL; duty cycle correction; eight core processor; embedded DRAM; flip flop design; high speed I O; L3 cache; latch; LBIST; microprocessor; multi core; multiport SRAM; POWER processor; POWER7; pulsed clock latch; quad threaded core; SER; SEU; SMP; SOI; vector register file; vector scalar unit

Indexed keywords

CLOCK GRID; CLOCKED STORAGE ELEMENTS; CML CIRCUITS; CORE PROCESSORS; DEBUG FEATURES; DEEP TRENCH CAPACITORS; DESIGN FOR RELIABILITY; DESIGN FOR TEST; DIFFERENTIAL I/O; DIGITAL PLL; DUTY CYCLE CORRECTION; EMBEDDED DRAM; FLIP-FLOP DESIGNS; HIGH SPEED I/O; L3 CACHE; LATCH; LBIST; MICROPROCESSOR; MULTI CORE; MULTI-PORT; POWER PROCESSORS; POWER7; PULSED-CLOCK LATCH; QUAD-THREADED CORE; SER; SEU; SMP; SOI;

EID: 78650855030     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2080611     Document Type: Conference Paper
Times cited : (47)

References (17)
  • 2
    • 77952142355 scopus 로고    scopus 로고
    • POWER7™ design
    • B. Starke, "POWER7™ design," in Hot Chips, 2009.
    • (2009) Hot Chips
    • Starke, B.1
  • 3
    • 77952179543 scopus 로고    scopus 로고
    • The implementation of POWER7™, a highly parallel, scalable multi-core high end server processor
    • D. Wendel et al., "The implementation of POWER7™, a highly parallel, scalable multi-core high end server processor," in IEEE ISSCC Dig. Tech. Papers, 2010.
    • (2010) IEEE ISSCC Dig. Tech. Papers
    • Wendel, D.1
  • 4
    • 34548845553 scopus 로고    scopus 로고
    • Implementation of the CELL broadband engine™ in a 65 nm SOI technology featuring dual-supply SRAM arrays supporting 6 GHz at 1.3 v
    • J. Pille et al., "Implementation of the CELL broadband engine™ in a 65 nm SOI technology featuring dual-supply SRAM arrays supporting 6 GHz at 1.3 V," in IEEE ISSCC Dig. Tech. Papers, 2007.
    • (2007) IEEE ISSCC Dig. Tech. Papers
    • Pille, J.1
  • 5
    • 33947259838 scopus 로고    scopus 로고
    • High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
    • S. Narasimha et al., "High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography," in IEDM, 2006.
    • (2006) IEEE ISSCC Dig. Tech. Papers
    • Narasimha, S.1
  • 6
    • 77952167003 scopus 로고    scopus 로고
    • A 32 kB 2R/1W L1 data cache in 45 nm SOI technology for the POWER7™ processor
    • 19.2
    • J. Pille et al., "A 32 kB 2R/1W L1 data cache in 45 nm SOI technology for the POWER7™ processor," in IEEE ISSCC Dig. Tech. Papers, 2010, 19.2.
    • (2010) IEEE ISSCC Dig. Tech. Papers
    • Pille, J.1
  • 7
    • 78650865418 scopus 로고    scopus 로고
    • The 3rd generation of IBM's elastic interface on POWER6™
    • Aug.
    • D. Dreps et al., "The 3rd generation of IBM's elastic interface on POWER6™," Hot Chips 19, Aug. 2007.
    • (2007) Hot Chips , vol.19
    • Dreps, D.1
  • 10
    • 45749133086 scopus 로고    scopus 로고
    • Circuit design and modeling for soft errors
    • May
    • A. J. KleinOsowski et al., "Circuit design and modeling for soft errors," IBM J. Res. Develop., vol. 52, pp. 255-263, May 2008.
    • (2008) IBM J. Res. Develop. , vol.52 , pp. 255-263
    • Kleinosowski, A.J.1
  • 11
    • 57849125602 scopus 로고    scopus 로고
    • SOI series MOSFET for embedded high voltage applications and soft-error immunity
    • Oct.
    • J. Cai et al., "SOI series MOSFET for embedded high voltage applications and soft-error immunity," in IEEE Int. SOI Conf. Proc., Oct. 2008, pp. 21-22.
    • (2008) IEEE Int. SOI Conf. Proc. , pp. 21-22
    • Cai, J.1
  • 12
    • 33746912373 scopus 로고    scopus 로고
    • Circuit design techniques for a first-generation cell broadband engine processor
    • Aug.
    • J. Warnock et al., "Circuit design techniques for a first-generation cell broadband engine processor," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1692-1706, Aug. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.8 , pp. 1692-1706
    • Warnock, J.1
  • 13
    • 2442641705 scopus 로고    scopus 로고
    • Timing uncertainty measurements on the Power5 microprocessor
    • Feb.
    • P. J. Restle, "Timing uncertainty measurements on the Power5 microprocessor," in IEEE ISSCC 2004 Dig. Tech. Papers, Feb. 2004, vol. 1, pp. 354-355.
    • (2004) IEEE ISSCC 2004 Dig. Tech. Papers , vol.1 , pp. 354-355
    • Restle, P.J.1
  • 14
    • 78650875707 scopus 로고    scopus 로고
    • Scaling deep trench based eDRAM on SOI to 32 nm and beyond
    • G. Wang et al., "Scaling deep trench based eDRAM on SOI to 32 nm and beyond," in IEDM, 2008.
    • (2008) IEEE ISSCC 2004 Dig. Tech. Papers
    • Wang, G.1
  • 15
    • 78650893115 scopus 로고    scopus 로고
    • A wide range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45 nm SOI
    • A. Rylyakov et al., "A wide range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45 nm SOI," in Proc. CICC, 2008.
    • (2008) Proc. CICC
    • Rylyakov, A.1
  • 16
    • 77952114209 scopus 로고    scopus 로고
    • A 45 nm SOI embedded DRAM macro for the POWER7™ processor 32 MByte on-chip L3 cache
    • paper 19.1
    • J. Barth et al., "A 45 nm SOI embedded DRAM macro for the POWER7™ processor 32 MByte on-chip L3 cache," in IEEE ISSCC Dig. Tech. Papers, 2010, paper 19.1.
    • (2010) IEEE ISSCC Dig. Tech. Papers
    • Barth, J.1
  • 17
    • 77952185922 scopus 로고    scopus 로고
    • POWER7™ local clocking and clocked storage elements
    • J. Warnock et al., "POWER7™ local clocking and clocked storage elements," in IEEE ISSCC Dig. Tech. Papers, 2010.
    • (2010) IEEE ISSCC Dig. Tech. Papers
    • Warnock, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.