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Volumn 46, Issue 1, 2011, Pages 145-161
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POWER7™, a highly parallel, scalable multi-core high end server processor
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IBM
(United States)
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Author keywords
clock grid; Clocked storage element design; CML circuits; debug features; deep trench capacitor; design for reliability; design for test; differential I O; digital PLL; duty cycle correction; eight core processor; embedded DRAM; flip flop design; high speed I O; L3 cache; latch; LBIST; microprocessor; multi core; multiport SRAM; POWER processor; POWER7; pulsed clock latch; quad threaded core; SER; SEU; SMP; SOI; vector register file; vector scalar unit
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Indexed keywords
CLOCK GRID;
CLOCKED STORAGE ELEMENTS;
CML CIRCUITS;
CORE PROCESSORS;
DEBUG FEATURES;
DEEP TRENCH CAPACITORS;
DESIGN FOR RELIABILITY;
DESIGN FOR TEST;
DIFFERENTIAL I/O;
DIGITAL PLL;
DUTY CYCLE CORRECTION;
EMBEDDED DRAM;
FLIP-FLOP DESIGNS;
HIGH SPEED I/O;
L3 CACHE;
LATCH;
LBIST;
MICROPROCESSOR;
MULTI CORE;
MULTI-PORT;
POWER PROCESSORS;
POWER7;
PULSED-CLOCK LATCH;
QUAD-THREADED CORE;
SER;
SEU;
SMP;
SOI;
ANALOG CIRCUITS;
CAPACITORS;
CLOCKS;
DIGITAL CIRCUITS;
DISTRIBUTED COMPUTER SYSTEMS;
DYNAMIC RANDOM ACCESS STORAGE;
FLIP FLOP CIRCUITS;
MICROPROCESSOR CHIPS;
SILICON ON INSULATOR TECHNOLOGY;
STATIC RANDOM ACCESS STORAGE;
VECTORS;
DESIGN;
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EID: 78650855030
PISSN: 00189200
EISSN: None
Source Type: Journal
DOI: 10.1109/JSSC.2010.2080611 Document Type: Conference Paper |
Times cited : (47)
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References (17)
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