Development of a thermal resistance model for chip-on-board packaging of high power LED arrays

Microelectronics Reliability

Volumn 52, Issue 5, 2012, Pages 836-844

  Ha, Minseok ^a   Graham, Samuel ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL EXPRESSIONS; CHIP-ON-BOARD; COMPUTATIONAL SIMULATION; DESIGN PARAMETERS; ELECTRONIC SUBSTRATES; HEAT SPREADING EFFECT; HIGH POWER LED; JUNCTION TEMPERATURES; LARGE HEAT FLUX; LED ARRAYS; LED PACKAGING; LIGHT INTENSITY; MATERIAL PROPERTY; OVERALL THERMAL RESISTANCE; SUBSTRATE THICKNESS;

CHIP SCALE PACKAGES; FINITE ELEMENT METHOD; HEAT RESISTANCE; THERMOANALYSIS;

LIGHT EMITTING DIODES;

EID: 84860357745     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2012.02.005     Document Type: Article

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