Fast, interactive worst-case execution time analysis with back-annotation

IEEE Transactions on Industrial Informatics

Volumn 8, Issue 2, 2012, Pages 366-377

  Harmon, Trevor ^a   Schoeberl, Martin ^b   Kirner, Raimund ^c   Klefstad, Raymond ^d   Kim, Kwang H ^f   Lowry, Michael R ^e  

^a INTEL CORPORATION   (United States)

^b DDTU Informatics   (Denmark)

^c UNIVERSITY OF HERTFORDSHIRE   (United Kingdom)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e NASA AMES RESEARCH CENTER   (United States)

^f NONE

Author keywords

Performance analysis; real time systems; safety; software algorithms; software performance; software reliability

Indexed keywords

DEVELOPMENT CYCLE; HARD REAL-TIME SYSTEMS; JAVA SOURCE; PATH ENUMERATION; PERFORMANCE ANALYSIS; PLUG-INS; PROGRAM SIZE; SOFTWARE ALGORITHMS; SOFTWARE PERFORMANCE; SOFTWARE PROGRAMMING; STATIC CODE ANALYSIS; TREE-BASED; TREE-BASED APPROACH; WCET CALCULATION; WORST-CASE EXECUTION TIME; WORST-CASE EXECUTION TIME ANALYSIS;

ACCIDENT PREVENTION; FORESTRY; SOFTWARE RELIABILITY;

REAL TIME SYSTEMS;

ALGORITHMS; COMPUTER PROGRAMING; COMPUTER PROGRAMS; PERFORMANCE; RELIABILITY; SAFETY;

EID: 84859918646     PISSN: 15513203     EISSN: None     Source Type: Journal    
DOI: 10.1109/TII.2012.2187457     Document Type: Article

References (59)

1. J. Engblom, A. Ermedahl, M. Sjoedin, J. Gustafsson, and H. Hansson, "Worst-case execution-time analysis for embedded real-time systems," Int. J. Softw. Tools Technol. Transfer, vol. 4, no. 4, pp. 437-455, Aug. 2003.
2. D. Hardy and I. Puaut, "WCET analysis of instruction cache hierarchies," J. Syst. Arch., vol. 57, no. 7, pp. 677-694, 2011.
3. R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand, "Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems," IEEE Trans. CAD of Integr. Circuits Syst., vol. 28, no. 7, pp. 966-978, 2009.
4. D. Grund, J. Reineke, and G. Gebhard, "Branch target buffers: WCET analysis framework and timing predictability," J. Syst. Arch., vol. 57, no. 6, pp. 625-637, 2011.
5. P. Puschner and A. Burns, "Guest editorial: A review of worst-case execution- time analysis," Real-Time Syst., vol. 18, no. 2-3, pp. 115-128, May 2000.
6. R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenström, "The worst-case execution time problem-Overview of methods and survey of tools," ACM Trans. Embedded Comput. Syst., vol. 7, no. 3, pp. 1-53, Apr. 2008.
7. S. Byhlin, A. Ermedahl, J. Gustafsson, and B. Lisper, "Applying static WCET analysis to automotive communication software," in Proc. 17th Euromicro Conf. Real-Time Syst. (ECRTS'05), Washington, DC, Jul. 2005, pp. 249-258. (Pubitemid 44458437)
8. J. Gustafsson and A. Ermedahl, "Experiences from applying WCET analysis in industrial settings," in Proc. 10th IEEE Int. Symp. Object and Component-Oriented Real-Time Distrib. Comput. (ISORC'07), Washington, DC, May 2007, pp. 382-392.
9. E. Gamma and K. Beck, Contributing to Eclipse: Principles, Patterns, and Plugins. Redwood City, CA: Addison-Wesley, 2003.
10. T. Harmon, M. Schoeberl, R. Kirner, and R. Klefstad, "Toward libraries for real-time Java," in Proc. 11th IEEE Int. Symp. Object Oriented Real-Time Distrib. Comput. (ISORC'08), May 2008, pp. 458-462.
11. R. Kirner and P. Puschner, "Discussion of misconceptions about WCET analysis," in Proc. 3rd Int. Workshop on Worst-Case Execution Time Anal. (WCET'03), Jul. 2003, pp. 61-64.
12. S. Altmeyer and C. M. Burguiere, "Cache-related preemption delay via useful cache blocks: Survey and redefinition," J. Syst. Arch., vol. 57, no. 7, pp. 707-719, 2011.
13. A. Ermedahl, F. Stappert, and J. Engblom, "Clustered worst-case execution- time calculation," IEEE Trans. Comput., vol. 54, no. 9, pp. 1104-1122, Sep. 2005. (Pubitemid 41387740)
14. J. Gustafsson and A. Ermedahl, "Merging techniques for faster derivation of WCET flow information using abstract execution," in Proc. 8th Int. Workshop on Worst-Case Execution Time Anal. (WCET'08), Prague, Czech Republic, Jul. 2008.
15. M. Schoeberl, "Time-predictable computer architecture," EURASIP J. Embedded Syst., vol. 2009, pp. 17-17, 2009, Article ID 758480.
16. J. M. O'Connor and M. Tremblay, "PicoJava-I: The Java virtual machine in hardware," IEEE Micro, vol. 17, no. 2, pp. 45-53, Mar./Apr. 1997. (Pubitemid 127559766)
17. M. Schoeberl, "A Java processor architecture for embedded real-time systems," J. Syst. Arch., vol. 54, no. 1-2, pp. 265-286, 2008. (Pubitemid 351608351)
18. L. Yan and Z. Liang, "An accelerator design for speedup of Java execution in consumer mobile devices," Compute. Elect. Eng., vol. 35, no. 6, pp. 904-919, 2009.
19. M. Schoeberl, "Application experiences with a real-time Java processor," in Proc. 17th IFAC World Congr., Seoul, Korea, Jul. 2008, pp. 9320-9325.
20. G. Michel and J. Sachtleben, "An integrated gyrotron controller," Fusion Eng. Design, vol. In Press, pp. 2011-2011.
21. R. Wilhelm, J. Engblom, S. Thesing, and D. Whalley, "Industrial requirements for WCET tools: Answers to the ARTIST questionnaire," in Proc. 3rd Int. Workshop on Worst-Case Execution Time Anal. (WCET'03), Jul. 2003, pp. 39-43.
22. S. Uhrig and J. Wiese, "Jamuth: An IP processor core for embedded Java real-time systems," in Proc. 5th Int. Workshop on Java Technol. Real-Time and Embedded Syst. (JTRES'07), New York, 2007, pp. 230-237. (Pubitemid 351203930)
23. J. Auerbach, D. F. Bacon, B. Blainey, P. Cheng, M. Dawson, M. Fulton, D. Grove, D. Hart, and M. Stoodley, "Design and implementation of a comprehensive real-time Java virtual machine," in Proc. 7th ACM and IEEE Int. Conf. Embedded Softw. (EMSOFT'07), New York, Sep. 2007, pp. 249-258. (Pubitemid 351203902)
24. A. Armbruster, J. Baker, A. Cunei, C. Flack, D. Holmes, F. Pizlo, E. Pla, M. Prochazka, and J. Vitek, "A real-time Java virtual machine with applications in avionics," Trans. Embedded Comput. Syst., vol. 7, no. 1, pp. 1-49, 2007.
25. C. Andreae, Y. Coady, C. Gibbs, J. Noble, J. Vitek, and T. Zhao, "Scoped types and aspects for real-time Java memory management," Real-Time Syst., vol. 37, no. 1, pp. 1-44, 2007. (Pubitemid 47235874)
26. C. Pitter and M. Schoeberl, "A real-time Java chip-multiprocessor, " ACM Trans. Embed. Comput. Syst., vol. 10, no. 1, pp. 9:1-34, 2010.
27. J. J. Hunt, I. Tonin, and F. B. Siebert, "Using global data flow analysis on bytecode to aid worst case execution time analysis for realtime Java programs," in Proc. 6th Int. Workshop Java Technol. Real-Time and Embedded Syst. (JTRES'08), New York, Sep. 2008, pp. 97-105.
28. J. H. Spring, F. Pizlo, J. Privat, R. Guerraoui, and J. Vitek, "Reflexes: Abstractions for integrating highly responsive tasks into Java applications," ACM Trans. Embedded Comput. Syst, vol. 10, no. 1, 2010.
29. M. Kim and A.Wellings, "Efficient asynchronous event handling in the real-time specification for java," ACM Trans. Embed. Comput. Syst., vol. 10, pp. 5:1-5:34, Aug. 2010.
30. T. Harmon and R. Klefstad, "Toward a unified standard for worst-case execution time annotations in real-time Java," in Proc. 15th Int. Workshop on Parallel and Distrib. Real-Time Syst. (WPDRTS'07), Mar. 2007.
31. H. Kopetz and G. Bauer, "The time-triggered architecture," Proc. IEEE, vol. 91, no. 1, pp. 112-126, Jan. 2003.
32. MISRA-C: Guidelines for the Use of the C Language in Critical Systems. : The Motor Industry Software Reliability Association (MISRA), 2004.
33. A. Colin and I. Puaut, "A modular and retargetable framework for treebased WCET analysis," in Proc. 13th Euromicro Conf. Real-Time Syst. (ECRTS'01), Washington, DC, Jun. 2001, pp. 37-44.
34. Y.-T. S. Li and S. Malik, "Performance analysis of embedded software using implicit path enumeration," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 16, no. 12, pp. 1477-1487, Dec. 1997. (Pubitemid 127765025)
35. S. Dasgupta, C. H. Papadimitriou, and U. Vazirani, Algorithms. New York: McGraw-Hill, 2008, ch. 7.
36. N. Holsti and S. Saarinen, "Status of the Bound-TWCET tool," in Proc. 2nd Int. Workshop on Worst-Case Execution Time Anal. (WCET'02), Jun. 2002.
37. C. Ferdinand and R. Heckmann, "Ait: Worst-case execution time prediction by static program analysis," in Building the Information Society, ser. IFIP International Federation for Information Processing. New York: Springer, 2004, vol. 156, pp. 377-383.
38. X. Li, Y. Liang, T. Mitra, and A. Roychoudhur, "Chronos: A timing analyzer for embedded software," Sci. Comput. Program., vol. 69, pp. 56-67, Dec. 2007. (Pubitemid 350087241)
39. P. Puschner and C. Koza, "Calculating the maximum execution time of real-time programs," Real-Time Syst., vol. 1, no. 2, pp. 159-176, Sep. 1989.
40. P. Altenbernd, "On the false path problem in hard real-time programs," in Proc. 8th Euromicro Workshop on Real-Time Syst. (EURWRTS 2006), Los Alamitos, CA, Jun. 1996, pp. 102-107.
41. A. Colin and I. Puaut, "Worst case execution time analysis for a processor with branch prediction," RTS, vol. 18, no. 2, pp. 249-274, May 2000.
42. A. Ermedahl, F. Stappert, and J. Engblom, "Clustered worst-case execution time calculation," IEEE Trans. Comput., vol. 54, no. 9, pp. 1104-1122, Sep. 2005. (Pubitemid 41387740)
43. A. Colin and G. Bernat, "Scope-tree: A program representation for symbolic worst-case execution time analysis," in Proc. 14th Euromicro Conf.n Real-Time Syst. (ECRTS 2002),Washington, DC, Jun. 2002, pp. 50-59.
44. M. Schoeberl, "A time predictable instruction cache for a Java processor," in On the Move to Meaningful Internet Systems 2004, ser. Lecture Notes in Computer Science, R. Meersman and Z. Tari, Eds. New York: Springer, 2004, vol. 3292, pp. 371-382. (Pubitemid 39736347)
45. M. Schoeberl and R. Pedersen, "WCET analysis for a Java processor," in Proc. 4th Int. Workshop on Java Technol. Real-Time Embedded Systems (JTRES'06), Oct. 2006, pp. 202-211. (Pubitemid 47142483)
46. J. Gustafsson, A. Ermedahl, C. Sandberg, and B. Lisper, "Automatic derivation of loop bounds and infeasible paths for WCET analysis using abstract execution," in Proc. 27th IEEE Real-Time Syst. Symp. (RTSS 2006), Rio de Janeiro, Brazil, Dec. 2006, pp. 57-66. (Pubitemid 351209718)
47. T. Chen, T. Mitra, A. Roychoudhury, and V. Suhendra, R.Wilhelm, Ed. , "Exploiting branch constraints without exhaustive path enumeration," in Proc. 5th Int.Workshop onWorst-Case Execution Time Anal., Palma de Mallorca, Jul. 2005, pp. 40-43.
48. T. Harmon, "Interactive worst-case execution time analysis of hard real-time systems," Ph.D. dissertation, Univ. California, Irvine, CA, 2009.
49. M. Schoeberl, W. Puffitsch, R. U. Pedersen, and B. Huber, "Worst-case execution time analysis for a Java processor," Software: Practice and Experience, vol. 40/6, pp. 507-542, 2010.
50. J. Gustafsson, "The worst case execution time tool challenge 2006," in Proc. 2nd Int. Symp. Leveraging Appl. Formal Methods, Verification and Validation (ISoLA'06), Paphos, Cyprus, Nov. 2006, pp. 233-240.
51. L. Ko, C. Healy, E. Ratliff, R. Arnold, D. Whalley, and M. Harmon, "Supporting the specification and analysis of timing constraints," in Proc. 2nd IEEE Real-Time Technol. Appl. Symp. (RTAS'96), Boston, MA, Jun. 1996, pp. 170-178.
52. J. R. P. Ribeiro, N. C. da Silva, and C. E. Morón, "A visual environment for the development of parallel real-time programs," in Proc. 12th Int. Parallel Process. Symp./9th Symp. Parallel Distrib. Process. (IPPS/SPDP'98), Mar. 1998, vol. 1388, pp. 994-1014.
53. R. Kirner, "Consideration of optimizing compilers in the context of WCET analysis," in Proc. Deutsche Informatiktage, Oct. 2000, pp. 123-126.
54. R. Kirner, R. Lang, G. Freiberger, and P. Puschner, "Fully automatic worst-case execution time analysis for Matlab/Simulink models," in Proc. 14th Euromicro Conf. Real-Time Syst., Vienna, Austria, Jun. 2002, pp. 31-40, Vienna Univ. Technol..
55. G. Bollella, B. Brosgol, P. Dibble, S. Furr, J. Gosling, D. Hardin, and M. Turnbull, The Real-Time Specification for Java, G. Bollella, Ed. Redwood City, CA: Addison-Wesley, 2000.
56. P. Persson and G. Hedin, "An interactive environment for real-time software development," in Proc. Technol. Object-Oriented Languages Syst. (TOOLS'00), Washington, DC, Jun. 2000, pp. 57-68.
57. G. Bernat and M. Bennett, "Identifying opportunities for worst-case execution time reduction in an avionics system," in Proc. 12th Int. Conf. Reliable Softw. Technol. (Ada-Europe 2007), Jun. 2007.
58. J. Fauster, R. Kirner, and P. Puschner, "Intelligent editor for writing WCET-oriented programs," in Proc. 3rd Int. Conf. Embedded Softw. (EMSOFT'03), Philadelphia, PA, Oct. 2003, pp. 190-205.
59. M. Nolin, J. Mäki-Turja, and K. Hänninen, "Achieving industrial strength timing predictions of embedded system behavior," in Proc. Int. Conf. Embedded Syst. Appl. (ESA'08), Las Vegas, NV, Jul. 2008.