-
1
-
-
0000039023
-
Calculating the maximum execution time of real-time programs
-
Puschner, P., Koza, C.: Calculating the maximum execution time of real-time programs. Real-Time Syst. 1 (1989) 159-176
-
(1989)
Real-time Syst.
, vol.1
, pp. 159-176
-
-
Puschner, P.1
Koza, C.2
-
2
-
-
84882618546
-
Bounding worst-case instruction cache performance
-
Arnold, R., Mueller, F., Whalley, D., Harmon, M.: Bounding worst-case instruction cache performance. In: IEEE Real-Time Systems Symposium. (1994) 172-181
-
(1994)
IEEE Real-time Systems Symposium.
, pp. 172-181
-
-
Arnold, R.1
Mueller, F.2
Whalley, D.3
Harmon, M.4
-
3
-
-
0029517739
-
Integrating the timing analysis of pipelining and instruction caching
-
Healy, C., Whalley, D., Harmon, M.: Integrating the timing analysis of pipelining and instruction caching. In: IEEE Real-Time Systems Symposium. (1995) 288-297
-
(1995)
IEEE Real-time Systems Symposium.
, pp. 288-297
-
-
Healy, C.1
Whalley, D.2
Harmon, M.3
-
4
-
-
0000940792
-
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
-
Lee, C.G., Hahn, J., Seo, Y.M., Min, S.L., Ha, R., Hong, S., Park, C.Y., Lee, M., Kim, C.S.: Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans. Comput. 47 (1998) 700-713
-
(1998)
IEEE Trans. Comput.
, vol.47
, pp. 700-713
-
-
Lee, C.G.1
Hahn, J.2
Seo, Y.M.3
Min, S.L.4
Ha, R.5
Hong, S.6
Park, C.Y.7
Lee, M.8
Kim, C.S.9
-
5
-
-
0029720109
-
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
-
Washington - Brussels - Tokyo, IEEE Computer Society Press
-
Busquets-Mataix, J.V., Wellings, A., Serrano, J.J., Ors, R., Gil, P.: Adding instruction cache effect to schedulability analysis of preemptive real-time systems. In: IEEE Real-Time Technology and Applications Symposium (RTAS '96), Washington - Brussels - Tokyo, IEEE Computer Society Press (1996) 204-213
-
(1996)
IEEE Real-time Technology and Applications Symposium (RTAS '96)
, pp. 204-213
-
-
Busquets-Mataix, J.V.1
Wellings, A.2
Serrano, J.J.3
Ors, R.4
Gil, P.5
-
6
-
-
6944231166
-
The influence of processor architecture on the design and results of WCET tools
-
Heckmann, R., Langenbach, M., Thesing, S., Wilhelm, R.: The influence of processor architecture on the design and results of WCET tools. Proceedings of the IEEE 91 (2003)
-
(2003)
Proceedings of the IEEE
, vol.91
-
-
Heckmann, R.1
Langenbach, M.2
Thesing, S.3
Wilhelm, R.4
-
7
-
-
16244388466
-
A method-level analysis of object-oriented techniques in Java
-
Department of Computer Science, NUI Maynooth, Ireland
-
Power, J., Waldron, J.: A method-level analysis of object-oriented techniques in Java. Technical report, Department of Computer Science, NUI Maynooth, Ireland (2002)
-
(2002)
Technical Report
-
-
Power, J.1
Waldron, J.2
-
8
-
-
0004302191
-
-
Morgan Kaufmann Publishers Inc., Palo Alto, CA 94303
-
Hennessy, J., Patterson, D.: Computer Architecture: A Quantitative Approach, 3rd ed. Morgan Kaufmann Publishers Inc., Palo Alto, CA 94303 (2002)
-
(2002)
Computer Architecture: A Quantitative Approach, 3rd Ed.
-
-
Hennessy, J.1
Patterson, D.2
-
10
-
-
0242628287
-
JOP: A Java optimized processor
-
Workshop on Java Technologies for Real-Time and Embedded Systems. Catania, Italy
-
Schoeberl, M.: JOP: A Java optimized processor. In: Workshop on Java Technologies for Real-Time and Embedded Systems. Volume LNCS 2889., Catania, Italy (2003) 346-359
-
(2003)
LNCS
, vol.2889
, pp. 346-359
-
-
Schoeberl, M.1
|