Modeling stress in silicon with TSVs and its effect on mobility

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 1, Issue 9, 2011, Pages 1328-1335

  Selvanayagam, Cheryl ^a   Zhang, Xiaowu ^a   Rajoo, Ranjan ^a   Pinjala, Damaruganath ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Finite element modelling; mobility; stresses; through silicon via

Indexed keywords

ACTIVE DEVICES; COEFFICIENTS OF THERMAL EXPANSIONS; ELECTRICAL CONNECTION; ELECTRICAL INTERCONNECTS; ELECTRICAL PERFORMANCE; ELECTRONIC PRODUCT; FINITE ELEMENT MODELING; FINITE ELEMENT MODELLING; INTERCONNECT CHIPS; JOINT RELIABILITY; SILICON SURFACES; SILICON THICKNESS; STACKING LAYERS; TEMPERATURE LOADINGS; THERMAL MISMATCH; THERMAL STRAIN; THROUGH-SILICON VIA;

CARRIER MOBILITY; COPPER; ELECTRIC CONNECTORS; STRAIN; STRESSES; INTEGRATED CIRCUIT MANUFACTURE;

SILICON WAFERS;

EID: 84859803677     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2011.2158002     Document Type: Article

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