Nonlinearities in thin-silicon die strength tests

Proceedings of Technical Papers - International Microsystems, Packaging, Assembly, and Circuits Technology Conference, IMPACT

Volumn , Issue , 2011, Pages 91-95

  Huang, P S ^a   Tsai, M Y ^a  

^a CHANG GUNG UNIVERSITY   (Taiwan)

Author keywords

Die strength; Nonlinearity; Pin on elastic foundation; Thin die; Three point bending

Indexed keywords

CONTACT NONLINEARITY; DIE STRENGTH; EDGE EFFECT; FITTING EQUATIONS; HIGH STRESS; IC WAFERS; LINEAR BEAM THEORY; LINEAR THEORY; MOMENT EQUILIBRIA; NONLINEAR FINITE ELEMENT METHOD; NONLINEARITY; PACKAGE SIZE; PIN-ON-ELASTIC-FOUNDATION; RELIABILITY TESTING; SEMICONDUCTOR PACKAGES; SILICON DIE; STRENGTH PREDICTION; STRESS MODES; STRESS STATE; TEST METHOD; THEORETICAL FORMULATION; THREE POINT BENDING; THREE-POINT BENDING TEST;

CONTROL NONLINEARITIES; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; MICROSYSTEMS; PACKAGING; SILICON WAFERS;

DIES;

EID: 84857616365     PISSN: 21505934     EISSN: 21505942     Source Type: Conference Proceeding    
DOI: 10.1109/IMPACT.2011.6117278     Document Type: Conference Paper

References (8)

1. Huang, P. S. and Tsai, M. Y.,"Pin-on-Elastic-Foundation Test for Silicon Die Strength Determination," The 11th EMAP Conference, International Conference on Electronic Materials and Packaging, Penang, Malaysia, 2009.
2. Ohtsuki A., "An Analysis of Large Deflections in A Symmetrical Three-Point Bending of Beam," Bulletin of JSME, Vol. 29, No. 253, pp. 1988-1995, July 1986.
3. Schoenfelder, S., Ebert, M., Landesberger, C., Bock, K., and Bagdahn, J., "Investigations of The Influence of Dicing Techniques on The Strength Properties of Thin Silicon," Microelectronics Reliability 47, pp. 168-178, 2007.
4. Wu, T. Y., Tsukada, Y., and Chen, W. T., "Materials and Mechanics Issues in Flip-Chip Organic Packaging," Proceedings of 46th Electronics and Computer Technology Conference, Orlando, FL, pp. 524-533, 1996.
5. Tsai, M. Y., Hsu, C. H., and Wang, C. T., "Investigation of Thermo-Mechanical Behaviors of Flip Chip BGA in IC Packaging," IEEE Transactions on Components, Packaging, and Technology, Part A, 27(3), pp. 568-576, 2004.
6. Hawkins, G., Berg, H., Mahalingam, M., Lewis, G., and Lofgran, L., "Measurement of Silicon Strength as Affected by Wafer Back Processing," International Reliability Physics Symposium Conference, pp. 216-223, 1987., Orlando, FL, pp. 524-533, 1996.
7. McLellan, N., Fan, N., Liu, S., Lau, K., and Wu, J., "Effect of Wafer Thinning Condition on the Roughness, Morphology and Fracture Strength of Silicon Die," Transaction of ASME, J. of Electronic Packaging, 126, pp. 110-114, 2004.
8. Tsai, M. Y., Chen, C. H. and Lin, C. S., "Test Methods for Silicon Die Strength," Transaction of ASME, J. of Electronic Packaging, Vol. 128, pp. 419-426, Dec. 2006.