On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 724-727

  Goren, D ^a   Zelikson, M ^a   Gordin, R ^a   Wagner, I A ^a   Barger, A ^a   Amir, A ^a   Livshitz, B ^a   Sherman, A ^a   Tretiakov, Y ^c   Groves, R ^b   Park, J ^b   Jordan, D ^c   Strang, S ^c   Singh, R ^c   Dickey, C ^c   Harame, D ^c  

^a IBM HAIFA RESEARCH LAB   (Israel)

^b IBM   (United States)

^c NONE

Author keywords

Interconnect; Modeling; Vlsi

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC LINES; FREQUENCY DOMAIN ANALYSIS; SILICON; SUBSTRATES;

SIGNAL DESIGN;

MICROPROCESSOR CHIPS;

EID: 0043136512     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/776014.776017     Document Type: Conference Paper

References (6)

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3. R. Gordin, D. Goren, and M. Zelikson, "Modeling of On-Chip Transmission Lines in High-Speed AMS Design - The Low Frequency Inductance Calculation", IEEE SPI conf., pp. 129-132, Pisa, May 2002.
4. D. Goren et al., "An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 GHz) On-chip Transmission Line Approach", DATE'02, Paris, 2002.
5. Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Figures of Merit to Characterize the Importance of On-Chip Inductance," IEEE Trans. VLSI, Vol. 7, No. 4, pp. 442-449, Dec. 1999.
6. M. Reinhold et. al., "A Fully-Integrated 40Gb/s Clock and Data Recovery / 1:4 DEMUX IC in SiGe Technology". Proc. ISSCC 2001, pp. 84-85, Feb. 2001.