Low resistive tungsten dual poly-metal gates with multi-diffusion barrier metals in high performance memory devices

Solid-State Electronics

Volumn 69, Issue , 2012, Pages 22-26

  Sung, Min Gyu ^a   Kim, Yong Soo ^b   Kim, Sook Joo ^a   Jeong, Ii Kyo ^b   Choi, Hak Soon ^b   Kim, Moon Su ^b   Kim, Heonho ^b   Park, Sung Ki ^a  

^a Hynix Semiconductor Inc   (South Korea)

^b University of Ulsan   (South Korea)

Author keywords

Diffusion barrier metal; Dual poly metal gate; Low resistivity tungsten; Ring oscillator signal delay

Indexed keywords

AMORPHOUS LAYER; BARRIER METALS; DIFFUSION BARRIER METALS; DUAL POLY-METAL GATE; GATE CONTACT; LOW POWER; RING OSCILLATOR;

DIFFUSION BARRIERS; TUNGSTEN;

RANDOM ACCESS STORAGE;

EID: 84857045915     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2011.09.003     Document Type: Article

References (14)

1. N.J. Son, Y. Oh, W. Kim, W.M. Jang, W. Yang, and G. Jin A unique dual-poly gate technology for 1.2-V mobile DRAM with simple in situ n+-doped polysilicon IEEE Trans Electron Dev 51 2004 1644 1652
2. Y. Akasaka, S. Suehiro, K. Nakajima, T. Nakasugi, K. Miyano, and K. Kasai Low-resistivity poly-metal gate electrode durable for high-temperature processing IEEE Trans Electron Dev 43 1996 1864 1869
3. T. Yamamshita, Y. Nishida, K. Hayashi, T. Eimori, M. Inuishi, and Y. Ohji W-polymetal gate with low W/poly-Si interface resistance for high-speed/high-density embedded memory Jpn J Appl Phys 43 4B 2004 1799 1803
4. M.G. Sung, K.Y. Lim, H.J. Cho, S.R. Lee, S.A. Jang, and Y.S. Kim Roles of Ti, TiN, and WN as interdiffusion barrier for tungsten dual polygate stack in memory devices Jpn J Appl Phys 46 4B 2007 2134 2138 (Pubitemid 47256736)
5. P.O. Shim, J.H. Choy, G.S. GiL, K.M. Kyung, and J.C. Park Process optimization of polymetal(W/WN/Polysilicon) gate and its impact on dynamic random-access memory chip performance in 0.14-μm technology J Electron Mater 31 2002 988 993 (Pubitemid 35355662)
6. Y.S. Kim, M.G. Sung, and S.K. Park Tungsten-dual polymetal technology for low resistive gate electrode Solid-State Electron 54 2010 650 653
7. G.W. Lee, H.D. Lee, K.Y. Lim, Y.S. Kim, H.S. Yang, and G.S. Cho Characterization of polymetal gate transistors with low-temperature atomic-layer-deposition-grown oxide spacer IEEE Electron Dev Lett 30 2 2009 181 184
8. x/WN diffusion barrier in memory device Jpn J Appl Phys 46 2007 7256 7262 (Pubitemid 350074886)
9. x/WN diffusion barrier for tungsten dual polymetal gate memory devices. IEEE 45th annual international reliability physics symposium (IRPS) 2007. p. 610-1. (Pubitemid 47432023)
10. H. Wakabayashi, T. Yamamoto, K. Yoshida, E. Soda, K.I. Tokunaga, and T. Mogami Ultralow resistance W/poly-Si gate CMOS technology using amorphous-Si/TiN buffer layer IEEE Trans Electron Dev 49 2 2002 295 300 (Pubitemid 34277203)
11. Y. Hiura, A. Azuma, K. Nakajima, Y. Akasaka, K. Miyano, and H. Nitta Integration technology of polymetal (W/WSiN/poly-Si) dual gate CMOS for 1Gbit DRAMs and Beyond Tech Dig - Int Electron Dev Meet (IEDM) 1998 389 392
12. x/poly-Si gate MOSFET for high density DRAM applications J Vac Sci Technol B23 3 2005 1036 1040 (Pubitemid 43127312)
13. A. Blosse, K. Ramkumar, P. Gopalan, C.T. Hsu, S. Narayanan, and C. Narasimhan A novel low cost 65 nm CMOS process architecture with self aligned isolation and W cladded source/drain Tech Dig -Int Electron Dev Meet (IEDM) 2004 669 672 (Pubitemid 40928381)
14. M.G. Sung, K.Y. Lim, H.J. Cho, Y.S. Kim, Y.T. Hwang, and S.A. Jang Dependence of gate interfacial resistance on the formation of insulative boron-nitride for p-channel metal-oxide-semiconductor field-effect transistor in tungsten dual polygate memory devices Jpn J Appl Phys 47 2008 2704 2709