Process optimization of polymetal (W/WN/polysilicon) gate and its impact on dynamic random-access memory chip performance in 0.14-μm Technology

Journal of Electronic Materials

Volumn 31, Issue , 2002, Pages 988-993

  Shim, Pil Bo ^a   Choy, Jun Ho ^a,b   Gil, Gyung Sun ^a   Kyung, Ki Myung ^a   Park, Ju Cheol ^a  

^a Hynix Semiconductor Inc   (South Korea)

^b SIMON FRASER UNIVERSITY   (Canada)

Author keywords

Data retention; Denudation; Diffusion barrier; DRAM; Polycide; Polymetal gate; Process integration; RC delay; Tungsten

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER SIMULATION; DIFFUSION; ELECTRIC SIGNAL SYSTEMS; ELECTRODES; OPTIMIZATION; POLYSILICON; TUNGSTEN;

DATA RETENTION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036809261     PISSN: 03615235     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11664-002-0032-8     Document Type: Article

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