Power efficient motion estimation algorithm and architecture based on pixel truncation

IEEE Transactions on Consumer Electronics

Volumn 57, Issue 4, 2011, Pages 1782-1790

  Chatterjee, Sumit K ^a   Chakrabarti, Indrajit ^b  

^a ASANSOL ENGINEERING COLLEGE   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

adaptive search pattern; fast two stage search algorithm; Low power design; pixel truncation; variable block size motion estimation architecture

Indexed keywords

ADAPTIVE SEARCH; BIT PLANES; BLOCK MATCHING ALGORITHMS; CONSUMER DEVICES; EARLY TERMINATION; LOW-POWER DESIGN; MEMORY MANAGEMENT; MEMORY MODULES; PIXEL RESOLUTION; POWER EFFICIENT; PROPOSED ARCHITECTURES; SEARCH ALGORITHMS; TWO STAGE; VARIABLE BLOCK-SIZE MOTION ESTIMATION; VLSI ARCHITECTURES;

ELECTRIC POWER SUPPLIES TO APPARATUS; ESTIMATION; LEARNING ALGORITHMS; MEMORY ARCHITECTURE; PIXELS;

MOTION ESTIMATION;

EID: 84856244853     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2011.6131154     Document Type: Article

References (18)

1. J. R. Jain and A. K. Jain, "Displacement measurement and its application in inter-frame image coding," IEEE Trans. Commun., vol. COM-29, pp. 1799-1808, Dec. 1981.
2. A. Netravali and J. D. Robbins, "Motion compensated television coding: Part I," Bell Syst. Tech. J., vol. 58, pp. 629-668, Apr. 1979.
3. F. Dufaux and F. Moscheni, "Motion estimation techniques for digital TV: A review and a new contribution," Proc. IEEE, vol. 83, pp. 858-876, June 1995.
4. L. M. Po and W. C. Ma, "A novel four-step search algorithm for fast block motion estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 6, no. 6, pp. 313-317, June 1996.
5. S. Zhu and K. K. Ma, "A new diamond search algorithm for fast block matching motion estimation," IEEE Trans. on Image Processing, vol. 9, no. 2, pp. 287-290, Feb. 2000. (Pubitemid 30557223)
6. Y. Nie and K. K. Ma, "Adaptive rood pattern search for fast block matching motion estimation," IEEE Trans. on Image Processing, vol. 11, no. 12, pp. 1442-1449, Dec. 2002.
7. B. Natarajan, V. Bhaskaran, and K. Konstantinides, "Low-complexity block-based motion estimation via one-bit transforms," IEEE Trans Circuits Syst. Video Technol., vol. 7, no. 8, pp. 702-706, Aug. 1997. (Pubitemid 127765233)
8. S. Ertürk, "Multiplication-free one-bit transform for low-complexity block-based motion estimation," IEEE Signal Process. Lett., vol. 14, no. 2, pp. 109-112, Feb. 2007. (Pubitemid 46351331)
9. Z. L. He, C. Y. Tsui, K. K. Chan, and M. L. Liou, "Low-power VLSI design for motion estimation using adaptive pixel truncation," IEEE Trans. Circuits Syst. Video Technol., vol. 10, no. 8, pp. 669-678, Aug. 2000.
10. A. Akin, Y. Dogan, and I. Hamzaoglu, "High performance hardware architectures for one bit transform based motion estimation," IEEE Trans. on Consumer Electron., vol. 55, no. 2, pp. 941-949, May 2009.
11. A. Akin, G. Sayilar, and I. Hamzaoglu, "High performance hardware architectures for one bit transform based single and multiple reference frame motion estimation," IEEE Trans. on Consumer Electron., vol. 56, no. 2, pp. 1144-1152, May 2010.
12. S. K. Chatterjee and I. Chakrabarti, "Low power VLSI architectures for one bit transformation based fast motion estimation," IEEE Trans. on Consumer Electron., vol. 56, no. 4, pp. 2652-2660, Nov. 2010.
13. A. Bahari, T. Arslan, and A. T. Erdogan, "Low-Power H.264 Video Compression Architectures for Mobile Communication," IEEE Trans. Circuits Syst. Video Technol., vol. 19, no. 9, pp. 1251-1261, Sept. 2009.
14. S. Lee, J. M. Kim, and S. I. Chae, "New motion estimation algorithm using adaptively quantized low bit-resolution image and its VLSI architecture for MPEG2 video encoding," IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 6, pp. 734-744, Oct. 1998. (Pubitemid 128743738)
15. C. Y. Chen, S. Y. Chien, Y. W. Huang, T. C. Chen, T. C. Wang, and L. G. Chen, "Analysis and architecture design of variable block size motion estimation for H.264/AVC," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 53, no. 3, pp. 578-593, Mar. 2006.
16. C. M. Ou, C. F. Le, and W. J. Hwang, "An efficient VLSI architecture for H.264 variable block size motion estimation," IEEE Trans. on Consumer Electron., vol. 51, no. 4, pp. 1291-1299, Nov. 2005.
17. T. C. Chen, Y. H. Chen, S. F. Tsai, S. Y. Chien, and L. G. Chen, "Fast algorithm and architecture design of low-power integer motion estimation for H.264/AVC," IEEE Trans. Circuits Syst. Video Technol., vol. 17, no. 5, pp. 568-577, May 2007.
18. Y. W. Huang, S. Y. Chien, B. Y. Hsieh, and L. G. Chen, "Global elimination algorithm and architecture for fast block matching motion estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 14, no. 6, pp. 898-907, Jun. 2004.