A framework for accelerating neuromorphic-vision algorithms on FPGAs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2011, Pages 810-813

  Debole, M ^a   Maashri, A Al ^a   Cotter, M ^a   Yu, C L ^a,b   Chakrabarti, C ^a,b   Narayanan, V ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b ARIZONA STATE UNIVERSITY   (United States)

Author keywords

FPGA application mapping; FPGA programming; Multi FPGA partitioning; Neuromorphic vision algorithms

Indexed keywords

FPGA APPLICATIONS; FPGA TECHNOLOGY; MULTI-FPGA; MULTI-FPGA SYSTEM; NEUROMORPHIC; OBJECT CLASSIFICATION;

ALGORITHMS; COMPUTER AIDED DESIGN;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84855778958     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105351     Document Type: Conference Paper

References (17)

1. Christopher Neely, Gordon Brebner, and weijia Shang, "ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs," in 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010, pp. 141-148.
2. (2007) Impulse C. [Online]. http://www.impulsec.com
3. (2007) The Mentor Graphics Web Page. [Online]. http://www.mentor.com/ products/esl/highlevelsynthesis/catapultsynthesis/
4. (2002) Cameron: Compiling high-level programs to fpga configurations. [Online]. http://www.cs.colostate.edu/cameron/
5. (2008) Calypto's sequential analysis technology. [Online]. http://www.calypto.com/
6. Xilinx. Xilinx Platform Studio. [Online]. www.xilinx.com
7. Xilinx. Xilinx System Generator. [Online]. www.xilinx.com
8. J. Cong et al., "High-Level Synthesis for FPGAs: From Prototyping to Deployment," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 4, pp. 473-491, April 2011.
9. Z. Zhang et al., "AutoPilot: A platform-based ESL synthesis system," in High-Level Synthesis: From Algorithm to Digital Circuit, P. Morawiec and A. Coussy, Eds. Heidelberg, Germany: Springer, 2008, ch. 6, pp. 99-112.
10. Maximilian Riesenhuber and Tomaso Poggio, "Hierarchical models of object recognition in cortex," Nature Neuroscience, vol. 2, no. 11, pp. 1019-1025, November 1999.
11. Jim Mutch and David G. Lowe, "Object class recognition and localization using sparse features with limited receptive fields," International Journal of Computer Vision (IJCV), vol. 80, no. 1, pp. 45-57, October 2008.
12. Jeffrey L Krichmar, Nikil Dutt, Jayram M Nageswaran, and Micah Richert, "Neuromorphic Modeling Abstractions and Simulation of Large-Scale Cortical Networks," in International Conference on Computer Aided Design (ICCAD), 2011.
13. Xilinx, "7 Series FPGAs Overview," DS180(v1.5) 2011.
14. Don Anderson and Tom Shanley, PCI Express System Architecture.: Addison-Wesley Professional, 2003.
15. Xilinx, "MicroBlaze Processor Referenc Guide Embedded Development Kit (EDK 11.1)," UG081 2009.
16. Kevin Irick et al., "A Scalable Multi-FPGA Framework for Real-Time Digital Signal Processing," in In Proceedings of SPIE, vol. 7444, 2009.
17. Nallatech Inc. (2011) [Online]. http://www.nallatech.com/Intel-Xeon-FSB- Socket-Fillers/fsb-development-systems.html