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Volumn 7444, Issue , 2009, Pages

A scalable multi-FPGA framework for real-time digital signal processing

Author keywords

FPGA design; Image processing

Indexed keywords

45NM TECHNOLOGY; ALGORITHMIC LEVELS; APPLICATION DEVELOPERS; APPLICATION PERFORMANCE; APPLICATION-SPECIFIC; CUSTOM CHIPS; DESIGN EFFORT; FPGA DESIGN; FPGA DESIGNERS; FUNCTIONAL DESIGN; GENERAL PURPOSE PROCESSORS; IMPROVING PERFORMANCE; LEVEL DESIGN; MULTI-FPGA; REAL-TIME DIGITAL SIGNAL PROCESSING; REAL-TIME SIGNAL PROCESSING; SIGNAL PROCESSING APPLICATIONS; SYSTEM INTEGRATORS; SYSTEM INTERFACES;

EID: 70350383770     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.834177     Document Type: Conference Paper
Times cited : (5)

References (7)
  • 1
    • 70350416718 scopus 로고    scopus 로고
    • Online] 2007
    • Impulsec. The Impulsec Web Page. [Online] 2007. http://www.impulsec.com,.
    • The Impulsec Web Page
  • 5
    • 34548835962 scopus 로고    scopus 로고
    • Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. S. Vasudevan, J. Abraham, V. Viswanath, and J. Tu. July 2006. Proceedings of International Conference on Formal Methods and Models for Co-Design (MEMOCODE '06). pp. 71-80.
    • Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. S. Vasudevan, J. Abraham, V. Viswanath, and J. Tu. July 2006. Proceedings of International Conference on Formal Methods and Models for Co-Design (MEMOCODE '06). pp. 71-80.
  • 7
    • 70350365970 scopus 로고    scopus 로고
    • Online] 2007
    • Sysgen. The Xilinx Web Page. [Online] 2007. http://www.xilinx.com/ ise/optionalprod/systemgenerator.htm.
    • The Xilinx Web Page
    • Sysgen1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.