Improved circuits for microchip identification using SRAM mismatch

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2011, Pages

  Chellappa, Srivatsan ^a   Dey, Aritra ^a   Clark, Lawrence T ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL FINGERPRINT; IMPROVED METHODS; PROCESS VARIATION; SECRET KEY; SERIAL NUMBER; SRAM CELL; TEST CHIPS;

DIGITAL INTEGRATED CIRCUITS; INTEGRATION; STATIC RANDOM ACCESS STORAGE;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 80455156107     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2011.6055318     Document Type: Conference Paper

References (13)

1. D. Kirovski, M. Drinic, and M. Potkonjak, "Enabling trusted software integrity". Proc. ASPLOS-X, San Jose, CA, Oct. 2002, pp. 108-120.
2. J. Lee, et al., "A technique to build a secret key in integrated circuits with identification and authentication applications", Proc. IEEE VLSI Circ. Symp., June 2004, pp. 176-179.
3. R. Glidden, et al., "Design of ultra-low-cost UHF RFID tags for supply chain applications", IEEE Comm. Mag., vol.42, no.8, pp. 140-151, Aug. 2004.
4. M. Alavi, et al., "A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process," Proc. IEDM, Dec. 1997, pp. 855-858.
5. G. Suh and S. Devadas, "Physical unclonable functions for device authentication and secret key generation", Proc. DAC, June 2007, pp. 9-14.
6. K. Lofstrom, W. Daasch, and D. Taylor, "IC identification circuit using device mismatch", Proc. ISSCC 2000, Feb 2000, pp 372-373.
7. B. Gassend, D. Clarke, M. Dijk and S. Devadas, "Delay-based circuit authentication and applications", Proc. ACM Symp. App. Comp., March 2003, pp 294-301.
8. Y. Su, J. Holleman, and B. Otis, "A digital 1. 6 pJ/bit chip identification circuit using process variations," IEEE J. Solid-state Circuits, vol.43, no.1, pp.69-77, Jan.2008.
9. D. Holcomb, W. Burleson, and K. Fu, "Power-up SRAM state as an identifying fingerprint and source of true random numbers", IEEE Trans. on Comp., vol. 58, pp.1198-1200, Sept. 2009.
10. A. Bhavnagarwala, T. Xinghai, and J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid- State Circ, vol. 36, no. 4, pp. 658-665, April 2001.
11. E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. 22, no. 5, pp. 748-754, Oct. 1987. (Pubitemid 18521731)
12. S. Chellappa, et al., "In-situ characterization and extraction of SRAM variability", Proc. DAC, June 2010, pp. 711-716.
13. K.Agarwal and S.Nassif, "Statistical analysis of SRAM cell stability,"in Proc. DAC, Sept 2006, pp. 57-62.