A low power fault-tolerance architecture for the kernel density estimation based image segmentation algorithm

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2011, Pages 161-168

  Li, Peng ^a   Lilja, David J ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Computer reliability; fault tolerance; image segmentation; logic design; low energy; low power; stochastic computing

Indexed keywords

COMPUTING CIRCUITS; DEVICE-SCALING; DIGITAL LOGIC GATES; FAULT TOLERANCE TECHNIQUES; IMAGE SEGMENTATION ALGORITHM; INPUT IMAGE; KERNEL DENSITY ESTIMATION; LOW ENERGIES; LOW POWER; LOWER-POWER CONSUMPTION; NANOSCALE DIMENSIONS; RANDOM BITS; SEGMENTATION PERFORMANCE; SOFT ERROR; STOCHASTIC COMPUTING; STOCHASTIC IMPLEMENTATION; TIME CONSTRAINTS; TRIPLE MODULAR REDUNDANCY;

ALGORITHMS; COMPUTER ARCHITECTURE; DIGITAL DEVICES; ERRORS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC DESIGN; LOGIC GATES; STOCHASTIC SYSTEMS;

IMAGE SEGMENTATION;

EID: 80055097490     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2011.6043264     Document Type: Conference Paper

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