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Volumn , Issue , 2008, Pages 132-137

Managing multi-core soft-error reliability through utility-driven cross domain optimization

Author keywords

[No Author keywords available]

Indexed keywords

CROSS-DOMAIN; MULTI CORES;

EID: 51649088958     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2008.4580167     Document Type: Conference Paper
Times cited : (15)

References (11)
  • 1
    • 27544494266 scopus 로고    scopus 로고
    • Techniques to Reduce the Soft Error Rate of A High Performance Microprocessor
    • C. Weaver et al., Techniques to Reduce the Soft Error Rate of A High Performance Microprocessor, In Proceedings of ISCA 2004
    • (2004) Proceedings of ISCA
    • Weaver, C.1
  • 2
    • 35348845144 scopus 로고    scopus 로고
    • Dynamic Prediction of Architectural Vulnerability From Microarchitectural State
    • K. R. Walcott et al., Dynamic Prediction of Architectural Vulnerability From Microarchitectural State, In Proceedings of ISCA 2007
    • (2007) Proceedings of ISCA
    • Walcott, K.R.1
  • 3
    • 0036287327 scopus 로고    scopus 로고
    • Detailed Design and Evaluation of Redundant Multithreading Alternatives
    • S. Mukherjee et al., Detailed Design and Evaluation of Redundant Multithreading Alternatives, In Proceedings of ISCA 2002
    • (2002) Proceedings of ISCA
    • Mukherjee, S.1
  • 4
    • 34548042910 scopus 로고    scopus 로고
    • Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
    • M. K. Qureshi et al., Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches, In Proceedings of MICRO 2006
    • (2006) Proceedings of MICRO
    • Qureshi, M.K.1
  • 5
    • 4544359318 scopus 로고    scopus 로고
    • A Systematic Methodology to Compute the Architectural Vulnerability Factors of a High-Performance Microprocessor
    • S.S. Mukherjee et al., A Systematic Methodology to Compute the Architectural Vulnerability Factors of a High-Performance Microprocessor, In Proceedings of ISCA 2003
    • (2003) Proceedings of ISCA
    • Mukherjee, S.S.1
  • 6
    • 27544458902 scopus 로고    scopus 로고
    • Computing Architectural Vulnerability Factors for Address-Based Structures
    • A. Biswas et al., Computing Architectural Vulnerability Factors for Address-Based Structures, In Proceedings of ISCA 2005
    • (2005) Proceedings of ISCA
    • Biswas, A.1
  • 8
    • 0345704209 scopus 로고    scopus 로고
    • Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Data-path Resources
    • D. Ponomarev et al, Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Data-path Resources, In Proceedings of MICRO 2001
    • (2001) Proceedings of MICRO
    • Ponomarev, D.1
  • 9
    • 51649096765 scopus 로고    scopus 로고
    • http://www.cs.binghamton.edu/~jsharke/m-sim/
  • 10
    • 85165864927 scopus 로고    scopus 로고
    • A Cost-Effective Implementation of an ECC-Protected Instruction Queue for Out-of-Order Microprocessors
    • V. Stojanovic et al., A Cost-Effective Implementation of an ECC-Protected Instruction Queue for Out-of-Order Microprocessors, In Proceedings of DAC 2006
    • (2006) Proceedings of DAC
    • Stojanovic, V.1
  • 11
    • 51649105263 scopus 로고    scopus 로고
    • V. K. Redd et al., Understanding Prediction-based Partial Redundant Threading for Low-Overhead, High-Coverage Fault Tolerance, In Proceedings of ASPLOS 2006
    • V. K. Redd et al., Understanding Prediction-based Partial Redundant Threading for Low-Overhead, High-Coverage Fault Tolerance, In Proceedings of ASPLOS 2006


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.