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Volumn , Issue , 2011, Pages 17-24

Address generation scheme for a coarse grain reconfigurable architecture

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS GENERATION; ADDRESS GENERATION UNITS; CIRCULAR BUFFER; COARSE GRAINS; COARSE-GRAIN RECONFIGURABLE ARCHITECTURES; DISTRIBUTED STORAGE RESOURCES; PROGRAMMABILITY; PROGRAMMABLE DELAY; RECONFIGURABLE ARCHITECTURE;

EID: 80055068421     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2011.6043232     Document Type: Conference Paper
Times cited : (18)

References (12)
  • 1
    • 53649099340 scopus 로고    scopus 로고
    • Address generation optimization for embedded high-performance processors: A survey
    • May
    • G. Talavera, M. Jayapala, J. Carrabina, and F. Catthoor, "Address generation optimization for embedded high-performance processors: A survey," fournal of Signal Processing Systems, vol. 53, pp. 271-284, May 2008.
    • (2008) Fournal of Signal Processing Systems , vol.53 , pp. 271-284
    • Talavera, G.1    Jayapala, M.2    Carrabina, J.3    Catthoor, F.4
  • 12
    • 77949370051 scopus 로고    scopus 로고
    • Partially reconfigurable interconnection network for dynamically reprogrammable resource array
    • M. A. Shami and A. Hemani, "Partially reconfigurable interconnection network for dynamically reprogrammable resource array," in Proc. IEEE 8th Int. Conf. ASIC ASICON '09, pp. 122-125, 2009.
    • (2009) Proc. IEEE 8th Int. Conf. ASIC ASICON '09 , pp. 122-125
    • Shami, M.A.1    Hemani, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.