![]() |
Volumn , Issue , 2011, Pages 17-24
|
Address generation scheme for a coarse grain reconfigurable architecture
|
Author keywords
[No Author keywords available]
|
Indexed keywords
ADDRESS GENERATION;
ADDRESS GENERATION UNITS;
CIRCULAR BUFFER;
COARSE GRAINS;
COARSE-GRAIN RECONFIGURABLE ARCHITECTURES;
DISTRIBUTED STORAGE RESOURCES;
PROGRAMMABILITY;
PROGRAMMABLE DELAY;
RECONFIGURABLE ARCHITECTURE;
DIGITAL SIGNAL PROCESSORS;
FIR FILTERS;
INDUCTIVE LOGIC PROGRAMMING (ILP);
PARALLEL PROCESSING SYSTEMS;
SIGNAL PROCESSING;
VERY LONG INSTRUCTION WORD ARCHITECTURE;
|
EID: 80055068421
PISSN: 10636862
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ASAP.2011.6043232 Document Type: Conference Paper |
Times cited : (18)
|
References (12)
|