Fine-grained energy consumption characterization and modeling

Proceedings - 2010 DoD High Performance Computing Modernization Program Users Group Conference, HPCMP UGC 2010

Volumn , Issue , 2011, Pages 487-497

  Olschanowsky, Catherine Mills ^a   Rosing, Tajana ^a   Snavely, Allan ^a   Carrington, Laura ^b   Tikir, Mustafa M ^b   Laurenzano, Michael ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE PREDICTION ERROR; COMPUTE RESOURCES; DATA LOCALITY; ENERGY COST; ENERGY MEASUREMENTS; ENERGY REQUIREMENTS; FINE-GRAINED POWER; HIGH-PERFORMANCE COMPUTING RESOURCES; NAS PARALLEL BENCHMARKS; PRIMARY SOURCES; TOTAL COST OF OWNERSHIP;

BENCHMARKING; COMPUTER SOFTWARE SELECTION AND EVALUATION; ENERGY UTILIZATION; SUPERCOMPUTERS;

COST BENEFIT ANALYSIS;

EID: 80053376945     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCMP-UGC.2010.54     Document Type: Conference Paper

References (27)

1. '06: Proceedings of the 2006 ACM/IEEE Conference on Supercomputing. New York, NY, USA: ACM, p. 230, 2006.
2. Post, D.E., "Guest editor's introduction: Computational science and engineering for the US Department of Defense." Computing in Science and Engineering, vol. 9, pp. 10-11, 2007. (Pubitemid 350025522)
3. Barroso, L.A. and U. Hölzle, "The case for energyproportional computing." Computer, vol. 40, no. 12, pp. 33-37, 2007.
4. Tikir, M., L. Carrington, E. Strohmaier, and A. Snavely, "A genetic algorithms approach to modeling the performance of memory-bound computations." Proceedings of SC07, Reno, NV, November 2007.
5. Carrington, L., M. Laurenzano, A. Snavely, R. Campbell, and L. Davis, "How well can simple metrics represent the performance of hpc applications?" Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005.
6. P.K., et al., "Exascale computing study: Technology challenges in exascale computing study: Technology challenges in achieving exascale systems." DARPA Tech. Rep., September 2008.
7. Lewis, A., S. Ghosh, and N.F. Tzeng, "Run-time energy consumption estimation based on workload in server systems." HotPower '08: Workshop on Power Aware Computing and Systems, December 2008.
8. Available, https://www.wattsupmeters.com/secure/index.php.
9. Available, http://sine.ni.com/nips/cds/view/p/lang/en/nid/203822.
10. Available, http://www.phidgets.com/index.php.
11. Snavely, A., L. Carrington, N. Wolter, J. Labarta, R. Badia, and A. Purkayastha, "A framework for application performance modeling and prediction." ACM/IEEE Conference on High Performance Networking and Computing, 2002.
12. Tikir, M., M. Laurenzano, L. Carrington, and A. Snavely, "The pmac binary instrumentation library for powerpc." Workshop on Binary Instrumentation and Applications, 2006.
13. Laurenzano, M.A., M.M. Tikir, L. Carrington, and A. Snavely, "Pebil: Efficient static binary instrumentation for linux." International Symposium on the Performance Analysis of Systems and Software, Mar.2#30.
14. Dhiman, G. and T.V. Rosing, "System-level power management using online learning." Trans. Comp.-Aided Des. Integ. Cir. Sys., vol. 28, no. 5, pp. 676-689, 2009.
15. Available, http://www.nas.nasa.gov/Resources/Software/npb.html, 2008.
16. Tiwari, V., S. Malik, A. Wolfe, and M.-C. Lee, "Instruction level power analysis and optimization of software." VLSI Design, Proceedings of the Ninth International Conference, pp. 326-328, Jan.1-36.
17. Tiwari, V., S. Malik, and A. Wolfe, "Power analysis of embedded software: a first step towards software power minimization." Very Large Scale Integration (VLSI) Systems, IEEE Transactions, vol. 2, no. 4, pp. 437-445, Dec.1-34.
18. Givargis, T., F. Vahid, and J. Henkel, "Fast cache and bus power estimation for parameterized system-on-a-chip design." Design, Automation and Test in Europe Conference and Exhibition Proceedings, pp. 333-338, 2000.
19. Simunic, T., L. Benini, and G.D. Micheli, "Energy-efficient design of battery-powered embedded systems." Special Issue of IEEE Transactions on VLSI, May 2001.
20. Li, Y. and J. Henkel, "A framework for estimating and minimizing energy dissipation of embedded HW/SW systems." Design Automation Conference Proceedings, pp. 188-193, June 1998.
21. Kapoor, B., "Low power memory architectures for video applications." VLSI: Proceedings of the 8th Great Lakes Symposium, pp. 2-7, Feb.1#38.
22. Landman, P. and J. Rabaey, "Activity-sensitive architectural power analysis." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, vol. 15, no. 6, pp. 571-587, June 1996. (Pubitemid 126776166)
23. Lajolo, M., A. Raghunathan, S. Dey, and L. Lavagno, "Efficient power co-estimation techniques for system-on-chip design." Design, Automation and Test in Europe Conference and Exhibition Proceedings, pp. 27-34, 2000.
24. Vijaykrishnan, N., M. Kandemir, M.J. Irwin, H.S. Kim, and W. Ye, "Energy-driven integrated hardware-software optimizations using simple power." SIGARCH Comput. Archit. News, vol. 28, no. 2, pp. 95-106, 2000.
25. Flinn, J. and M. Satyanarayanan, "Powerscope: a tool for profiling the energy usage of mobile applications." Mobile Computing Systems and Applications, Proceedings WMCSA '99, pp. 2-10, Feb.1#39.
26. Sinha, A. and A.P. Chandrakasan, "Jouletrack: a web based tool for software energy profiling." DAC '01: Proceedings of the 38th Annual Design Automation Conference, New York, NY, pp. 220-225, 2001. (Pubitemid 32840955)
27. Gurumurthi, S., A. Sivasubramaniam, M. Irwin, N. Vijaykrishnan, and M. Kandemir, "Using complete machine simulation for software power estimation: the softwatt approach." High-Performance Computer Architecture, Proceedings, Eighth International Symposium, pp. 141-150, Feb. 2002.