Fast cache and bus power estimation for parameterized system-on-a-chip design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 333-338

  Givargis, Tony D ^a   Vahid, Frank ^a   Henkel, Jörg ^b  

^a University of California Riverside   (United States)

^b NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVITY; FAST ESTIMATION; POWER CONSUMED; POWER ESTIMATIONS; RELATIVE ACCURACY; SEARCH HEURISTICS; SYSTEM-ON-A-CHIP DESIGNS; TWO-STEP APPROACH;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUSES; EXHIBITIONS; HEURISTIC ALGORITHMS;

DESIGN;

EID: 0010834395     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840292     Document Type: Conference Paper

References (26)

1. Chern et al., Multilevel metal capacitance models for CAD design synthesis systems, IEEE Electron Device Letters, vol. 13, Jan. 1992.
2. J. L. da Silva Jr, F. Catthoor, D. Verkest and H. De Man. Trading-off Power versus Area through a Parameterizable Model for Virtual Memory Management, IEEE VOLTA, 1999.
3. R. J. Evans, P. D. Franzon. Energy Consumption Modeling and Optimization for SRAMs, IEEE Journal of Solid-State Circuits, Vol. 30, No. 5, pp. 571-579, 1995.
4. W. Fornaciari, D. Sciuto, C. Silvano. Power Estimation for Architectural Exploration of HW/SW Communication on System- Level Buses, International Workshop on Hardware/Software Codesign, pp. 152-156, 1999.
5. D. Gajski, N. Dutt, C. Wu, S. Lin. High-Level Synthesis, Kluwer Academic Publishers, 1992.
6. T. Givargis and F. Vahid. Interface Exploration for Reduced Power in Core-Based Systems, International Synposium on System Synthesis, 1998, pp. 117-122.
7. T. Givargis, J. Henkel, and F. Vahid. Interface and Cache Power Exploration for Core - Based Embedded System Design. ICCAD 1999.
8. R. Gupta and Y. Zorian. Introducing Core-Based System Design, IEEE Design & Test, Vol. 14, No. 4, Oct-Dec 1997, pp. 15-25.
9. D. Kirovski, C. Lee, M. Potkonjak, and W. Mangione-Smith. Synthesis of Power Efficient Systems-on-Silicon, ASP-DAC 1998, pp. 557-562.
10. M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, A. Sangiovanni- Vincentelli. Efficient Power Estimation Techniques for HW/SW Systems, IEEE VOLTA, 1999.
11. Y. Li and J. Henkel. A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems, Design Automation Conference, pp. 188-193, 1998.
12. Mircea R. Stan and Wayne P. Burleson, Bus-Invert Coding for Low Power I/O, IEEE Transactions on VLSI, March 1995.
13. R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger. Evaluation Techniques for Storage Hierarchies, IBM Systems Journal, 9(2), pp. 78-117, 1970.
14. S. Ortiz. New Chips Move Networking onto Silicon. IEEE Computer, Feb 1999.
15. P. Panda and N. Dutt, Reducing address bus transition for low power memory mapping, European Design and Test Conference, pp. 63-68, 1996.
16. B. Payne. Rapid Silicon Prototyping: Paradigm for Custom Systemon- a-Chip Design, http://www.vlsi. com/velocity, 1998.
17. A. Raghunathan, N. K. Jha and S. Dey. High-level Power Analysis and Optimization. Kluwer Academic Publishers, Norwell, MA, 1998.
18. Semiconductor Industry Association Roadmap 1997, http://notes. sematech.org/ntrs/PublNTRS. nsf.
19. C. Su, A. Despain. Cache design trade-offs for power and performance optimization: a case study. International Symposium on Low Power Design, pp. 63-68, 1995.
20. F. Vahid, T. Givargis, The Case for a Configure-and- Execute Paradigm. International Workshop on Hardware/Software Codesign, 1999.
21. P. van der Wolf, P. Lieverse, M. Goel, D. L. Hei, K. Vissers. An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology, pp. 33-37, International Workshop on Hardware/Software Codesign, 1999.
22. J. van Meerbergen, A. Timmer, J. Leijten, F. Harmsze, M. Strik. Experiences with System Level Design for Consumer ICs, VLSI'98, pp 17-22.
23. Velocity product information, VLSI Technology Inc., http://www.vlsi. com/velocity.
24. Virtual Socket Interface Association, Architecture Document, http://www.vsi.org, 1997.
25. S. J. E. Wilton and N. P. Jouppi. CACTI: An Enhanced Cache Access and Cycle Time Model, IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, pp. 677-688, 1996.
26. Z. Wu and W. Wolf. Iterative Cache Simulation of Embedded CPUs with Trace Stripping. International Workshop on Hardware/Software Codesign, pp. 95-99, 1999.