Low power digital PLL based TDC using low rate clocks

Electronics Letters

Volumn 47, Issue 14, 2011, Pages 793-794

  Park, M J ^a   Lee, J Y ^b   Boo, H H ^b   Mhin, B H ^b   Kim, S D ^b   Park, M Y ^b   Lee, C S ^a   Yu, H K ^b  

^a Hanbat National University   (South Korea)

^b Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; ALL DIGITAL PHASE LOCKED LOOP; CLOCK PERIOD; DIGITAL PLL; DIGITALLY CONTROLLED OSCILLATORS; LOW POWER; LOW RATES; METASTABILITIES; REFERENCE CLOCK; TIME TO DIGITAL CONVERTERS; TIME-DIFFERENCES;

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; FREQUENCY CONVERTERS; JITTER; PHASE LOCKED LOOPS;

CLOCKS;

EID: 80053230013     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el.2011.1426     Document Type: Article

References (5)

1. Staszewski, R.B.: et al. ' 1.3V 20ps time-to-digital converter for frequency synthesis in 90-nm CMOS ', IEEE Trans. Circuits Syst. II, 2006, 53, (3), p. 220-224 10.1109/TCSII.2005.858754 1057-7130
2. Staszewski, R.B.: et al. ' All-digital PLL and transmitter for mobile phones ', IEEE J. Solid-State Circuits, 2005, 40, (12), p. 2469-2482 10.1109/JSSC.2005.857417 0018-9200
3. Lee, M.: et al. ' A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution ', IEEE J. Solid-State Circuits, 2009, 44, (10), p. 2808-2816 10.1109/JSSC.2009.2028753 0018-9200
4. Liu, D.: et al. ' Trading speed for low power by choice of supply and threshold voltage ', IEEE J. Solid-State Circuits, 1993, 28, (1), p. 10-17 10.1109/4.179198 0018-9200
5. Lee, S.-K.: et al. ' A 1GHz ADPLL with a 1.25ps minimum-resolution sub exponent TDC in 0.18m CMOS ', IEEE J. Solid-State Circuits, 2010, 45, (12), p. 2874-2881 10.1109/JSSC.2010.2077110 0018-9200