Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

International Journal of Circuit Theory and Applications

Volumn 39, Issue 9, 2011, Pages 963-972

  Lopich, Alexey ^a   Dudek, Piotr ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

asynchronous image processing; asynchronous logic; cellular processor; vision chip; wave computations

Indexed keywords

ASYNCHRONOUS LOGIC; CELLULAR PROCESSOR ARRAY; CELLULAR PROCESSORS; CMOS PROCESSS; CO-PROCESSORS; CONTINUOUS TIME; FOCAL PLANES; GLOBAL OPERATIONS; HOLE FILLING; IMAGE-PROCESSING ALGORITHMS; LOGIC NETWORKS; LOW-POWER CONSUMPTION; OBJECT RECONSTRUCTION; OPERATIONAL PERFORMANCE; PARALLEL ARRAYS; PROOF OF CONCEPT; VISION CHIP;

ASYNCHRONOUS SEQUENTIAL LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTER VISION; CRACK PROPAGATION; GENERAL PURPOSE COMPUTERS;

LOGIC CIRCUITS;

EID: 80053187756     PISSN: 00989886     EISSN: 1097007X     Source Type: Journal    
DOI: 10.1002/cta.679     Document Type: Article

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