An Asynchronous Cellular Logic Network for Trigger-Wave Image Processing on Fine-Grain Massively Parallel Arrays

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 5, 2006, Pages 354-358

  Dudek, Piotr ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

Cellular arrays; image processing; parallel archi; tectures; VLSI

Indexed keywords

ALGORITHMS; ASYNCHRONOUS SEQUENTIAL LOGIC; DATA REDUCTION; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; TRIGGER CIRCUITS; VLSI CIRCUITS;

ASYNCHRONOUS CELLULAR LOGIC NETWORK; PARALLEL ARRAYS; PROCESSOR-PER-PIXEL DATA ARRAYS; SINGLE-INSTRUCTION DATA ARRAYS; TRIGGER-WAVE IMAGE PROCESSING;

LOGIC CIRCUITS;

EID: 33646866538     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.869916     Document Type: Article

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