A dynamically reconfigurable SIMD processor for a vision chip

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 1, 2004, Pages 265-268

  Komuro, Takashi ^a   Kagami, Shingo ^a   Ishikawa, Masatoshi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

High speed image processing; Massively parallel processing; Reconfigurable; Single instruction multiple data (SIMD); Vision chip

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; IMAGE PROCESSING; PARALLEL PROCESSING SYSTEMS;

IMAGE PROCESSORS; SINGLE INSTRUCTION MULTIPLE DATA PROCESSOR; VISION CHIP;

INTEGRATED CIRCUIT LAYOUT;

EID: 0742286333     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.820876     Document Type: Article

References (5)

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4. T. Komuro, I. Ishii, M. Ishikawa, and A. Yoshida, "A digital vision chip specialized for high-speed target tracking," IEEE Trans. Electron Devices, vol. 50, pp. 191-199, Jan. 2003.
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