Processes scheduling on heterogeneous multi-core architecture with hardware support

Proceedings - 6th IEEE International Conference on Networking, Architecture, and Storage, NAS 2011

Volumn , Issue , 2011, Pages 236-241

  Hao, Shouqing ^a,b,c,d   Liu, Qi ^a,b,d   Zhang, Longbing ^a,b,d   Wang, Jian ^a,b,d  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

^b INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^c UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

^d Loongson Technology Corporation Limited   (China)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE SUPPORTS; HETEROGENEOUS MULTICORE; LATENCY-AWARE; LINUX KERNEL; MEMORY ACCESS; MEMORY ACCESS DELAY; MISS-RATE; MULTI CORE; MULTI-PROCESSORS; PAPER SUPPLY; PERFORMANCE COUNTERS; PERFORMANCE EVALUATION;

COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS;

SCHEDULING ALGORITHMS;

EID: 80052888064     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NAS.2011.26     Document Type: Conference Paper

References (15)

1. M. D. Hill and M. R. Marty, "Amdahl's law in the multicore era," Computer, vol. 41, no. 7, pp. 33-38, 2008.
2. E. Grochowski, R. Ronen, J. Shen, and H. Wang, "Best of both latency and throughput," in ICCD '04: Proceedings of the IEEE International Conference on Computer Design. Washington, DC, USA: IEEE Computer Society, 2004, pp. 236-243. (Pubitemid 40557113)
3. R. Kumar, K. Farkas, N. Jouppi, P. Ranganathan, and D. Tullsen, "Single-isa heterogeneous multi-core architectures: the potential for processor power reduction," in Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on, 3-5 2003, pp. 81 - 92.
4. R. Kumar, D. Tullsen, P. Ranganathan, N. Jouppi, and K. Farkas, "Single-isa heterogeneous multi-core architectures for multithreaded workload performance," in Computer Architecture, 2004. Proceedings. 31st Annual International Symposium on, 19-23 2004, pp. 64 - 75.
5. J. Mogul, J. Mudigonda, N. Binkert, P. Ranganathan, and V. Talwar, "Using asymmetric single-isa cmps to save energy on operating systems," Micro, IEEE, vol. 28, no. 3, pp. 26-41, may-june 2008.
6. E. Humenay, D. Tarjan, and K. Skadron, "Impact of process variations on multicore performance symmetry," in Proceedings of the conference on Design, automation and test in Europe, ser. DATE '07. San Jose, CA, USA: EDA Consortium, 2007, pp. 1653-1658. (Pubitemid 47334201)
7. R. Teodorescu and J. Torrellas, "Variation-aware application scheduling and power management for chip multiprocessors," in Computer Architecture, 2008. ISCA '08. 35th International Symposium on, 21-25 2008, pp. 363-374.
8. D. Shelepov, J. C. Saez Alcaide, S. Jeffery, A. Fedorova, N. Perez, Z. F. Huang, S. Blagodurov, and V. Kumar, "Hass: a scheduler for heterogeneous multicore systems," SIGOPS Oper. Syst. Rev., vol. 43, no. 2, pp. 66-75, 2009.
9. D. Koufaty, D. Reddy, and S. Hahn, "Bias scheduling in heterogeneous multi-core architectures," in EuroSys '10: Proceedings of the 5th European conference on Computer systems. New York, NY, USA: ACM, 2010, pp. 125-138.
10. T. Li, D. Baumberger, D. A. Koufaty, and S. Hahn, "Efficient operating system scheduling for performance-asymmetric multi-core architectures," in Supercomputing, 2007. SC '07. Proceedings of the 2007 ACM/IEEE Conference on, 10-16 2007, pp. 1-11.
11. T. Li, P. Brett, R. Knauerhase, D. Koufaty, D. Reddy, and S. Hahn, "Operating system support for overlapping-isa heterogeneous multi-core architectures," in High Performance Computer Architecture (HPCA), 2010 IEEE 16th International Symposium on, 9-14 2010, pp. 1-12.
12. W. Hu, J. Wang, X. Gao, Y. Chen, Q. Liu, and G. Li, "Godson-3: A scalable multicore risc processor with ×86 emulation," Micro, IEEE, vol. 29, no. 2, pp. 17-29, 2009.
13. B. Fan, L. Yang, Z. Gao, F. Zhang, and R. Wang, "The implementation and design methodology of a quad-core version godson-3 microprocessor," in Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on, 2009, pp. 1167-1170.
14. M. Becchi and P. Crowley, "Dynamic thread assignment on heterogeneous multiprocessor architectures," in CF '06: Proceedings of the 3rd conference on Computing frontiers. New York, NY, USA: ACM, 2006, pp. 29-40.
15. S. Balakrishnan, R. Rajwar, M. Upton, and K. Lai, "The impact of performance asymmetry in emerging multicore architectures," in Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on, 4-8 2005, pp. 506 - 517. (Pubitemid 41543466)