Column-selection-enabled 8T SRAM array with 1R/1W multi-port operation for DVFS-enabled processors

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2011, Pages 303-308

  Park, Sang Phill ^a   Kim, Soo Youn ^a   Lee, Dongsoo ^a   Kim, Jae Joon ^b   Griffin, W Paul ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

8T SRAM; Cache Memory; DVFS; Low Power

Indexed keywords

45NM TECHNOLOGY; 8T SRAM; DUAL PORT; DVFS; LOW POWER; MULTI-PORT; SIMULATION RESULT; WRITE-BACK;

CACHE MEMORY; COMPUTER ARCHITECTURE; LOW POWER ELECTRONICS; POWER ELECTRONICS;

STATIC RANDOM ACCESS STORAGE;

EID: 80052738119     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2011.5993654     Document Type: Conference Paper

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