메뉴 건너뛰기




Volumn , Issue , 2011, Pages 186-187

3D integration from the viewpoint of high-end server system design

Author keywords

3D; 3D architecture; 3D design; 3DI

Indexed keywords

3-D INTEGRATION; 3D; 3D ARCHITECTURES; 3D DESIGN; 3DI; CO-DESIGN APPROACH; COMPUTATIONAL DENSITY; HIGH PERFORMANCE APPLICATIONS; HIGH-END SERVERS; MULTI-DISCIPLINARY; POTENTIAL BENEFITS; SERVER SYSTEM;

EID: 80052686294     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (8)
  • 1
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A novel chip design for improving deep sub-micrometer interconnect performance and systems-on-chip integration
    • K. Banerjee, S. Souri, P. Kapur, K. Saraswat, "3-D ICs: a novel chip design for improving deep sub-micrometer interconnect performance and systems-on-chip integration", Proceedings of IEEE 89, pp. 602-603, 2001
    • (2001) Proceedings of IEEE , vol.89 , pp. 602-603
    • Banerjee, K.1    Souri, S.2    Kapur, P.3    Saraswat, K.4
  • 3
    • 0036928172 scopus 로고    scopus 로고
    • Electrical integrity of state-of-the-art 0.13um SOI CMOS devices and circuits transferred for three-dimensional integrated circuit fabrication
    • K.W. Guarini et al., "Electrical integrity of state-of-the-art 0.13um SOI CMOS devices and circuits transferred for three-dimensional integrated circuit fabrication", Proceedings Of International Electron Devices Meeting, pp.943-945, 2002
    • (2002) Proceedings of International Electron Devices Meeting , pp. 943-945
    • Guarini, K.W.1
  • 4
    • 33845593337 scopus 로고    scopus 로고
    • Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology
    • J.U. Knickerbocker et al., "Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology", IEEE Custom Integrated Circuits Conference, pp. 659-662, 2005
    • (2005) IEEE Custom Integrated Circuits Conference , pp. 659-662
    • Knickerbocker, J.U.1
  • 6
    • 46049098824 scopus 로고    scopus 로고
    • 3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10um pitch through-Si-vias
    • N. Swinnen et al., "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10um pitch through-Si-vias", IEEE International Electron Devices Meeting, pp.1-4, Issue 11, 2006
    • (2006) IEEE International Electron Devices Meeting , Issue.11 , pp. 1-4
    • Swinnen, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.