-
1
-
-
33747566850
-
3-D ICs: A novel chip design for improving deep sub-micrometer interconnect performance and systems-on-chip integration
-
K. Banerjee, S. Souri, P. Kapur, K. Saraswat, "3-D ICs: a novel chip design for improving deep sub-micrometer interconnect performance and systems-on-chip integration", Proceedings of IEEE 89, pp. 602-603, 2001
-
(2001)
Proceedings of IEEE
, vol.89
, pp. 602-603
-
-
Banerjee, K.1
Souri, S.2
Kapur, P.3
Saraswat, K.4
-
2
-
-
64349118463
-
A wafer-scale 3-D circuit integration technology
-
J.A. Burns, C. K. Chen, J. M. Knect, P. W. Wyatt, "A wafer-scale 3-D circuit integration technology, IEEE Trans. on Electron Devices, Vol.53, No.10, pp. 2507-2516, 2006
-
(2006)
IEEE Trans. on Electron Devices
, vol.53
, Issue.10
, pp. 2507-2516
-
-
Burns, J.A.1
Chen, C.K.2
Knect, J.M.3
Wyatt, P.W.4
-
3
-
-
0036928172
-
Electrical integrity of state-of-the-art 0.13um SOI CMOS devices and circuits transferred for three-dimensional integrated circuit fabrication
-
K.W. Guarini et al., "Electrical integrity of state-of-the-art 0.13um SOI CMOS devices and circuits transferred for three-dimensional integrated circuit fabrication", Proceedings Of International Electron Devices Meeting, pp.943-945, 2002
-
(2002)
Proceedings of International Electron Devices Meeting
, pp. 943-945
-
-
Guarini, K.W.1
-
4
-
-
33845593337
-
Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology
-
J.U. Knickerbocker et al., "Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology", IEEE Custom Integrated Circuits Conference, pp. 659-662, 2005
-
(2005)
IEEE Custom Integrated Circuits Conference
, pp. 659-662
-
-
Knickerbocker, J.U.1
-
5
-
-
84948471389
-
Fabrication technologies for three-dimensional integrated circuits
-
R. Reif, A.Fan, C.Kuan-Neng, S.Das, "Fabrication technologies for three-dimensional integrated circuits", IEEE International Symposium on Quality-Aware Electronic Design, pp. 33-37, 2002
-
(2002)
IEEE International Symposium on Quality-Aware Electronic Design
, pp. 33-37
-
-
Reif, R.1
Fan, A.2
Kuan-Neng, C.3
Das, S.4
-
6
-
-
46049098824
-
3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10um pitch through-Si-vias
-
N. Swinnen et al., "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10um pitch through-Si-vias", IEEE International Electron Devices Meeting, pp.1-4, Issue 11, 2006
-
(2006)
IEEE International Electron Devices Meeting
, Issue.11
, pp. 1-4
-
-
Swinnen, N.1
-
7
-
-
47849132667
-
Three-dimensional chip-multiprocessor run-time thermal management
-
C. Zhu, Z.Gu, Li Shang, R.P. Dick, R. Joseph, "Three-dimensional chip-multiprocessor run-time thermal management", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol.27, No.8, 2008
-
(2008)
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
, vol.27
, Issue.8
-
-
Zhu, C.1
Gu, Z.2
Shang, L.3
Dick, R.P.4
Joseph, R.5
-
8
-
-
16244385917
-
A thermal-driven floorplanning algorithm for 3D ICs
-
J.Cong, J.Wei, Y.Zhang, "A thermal-driven floorplanning algorithm for 3D ICs", IEEE International Conference on Computer Aided Design, pp.306-313, 2004
-
(2004)
IEEE International Conference on Computer Aided Design
, pp. 306-313
-
-
Cong, J.1
Wei, J.2
Zhang, Y.3
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