Fine-grained power-gating scheme of a metal-oxide-semiconductor and magnetic-tunnel-junction-hybrid bit-serial ternary content-addressable memory

Japanese Journal of Applied Physics

Volumn 49, Issue 4 PART 2, 2010, Pages

  Matsunaga, Shoun ^a   Natsui, Masanori ^a   Hiyama, Kimiyuki ^a   Endoh, Tetsuo ^a   Ohno, Hideo ^a   Hanyu, Takahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-SERIAL; CUT-OFF; FINE-GRAINED POWER; LOW POWER; METAL OXIDE SEMICONDUCTOR; POWER SUPPLY; POWER-DELAY PRODUCTS; SEARCH OPERATIONS; STANDBY MODE; STANDBY-POWER DISSIPATION; TERNARY CONTENT ADDRESSABLE MEMORIES;

CMOS INTEGRATED CIRCUITS; DIELECTRIC DEVICES; ELECTRIC CONVERTERS; LOGIC GATES; MAGNETIC STORAGE; MOS DEVICES;

SEMICONDUCTOR JUNCTIONS;

EID: 77952699533     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.49.04DM05     Document Type: Article

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