Process-level virtualization for runtime adaptation of embedded software

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 895-900

  Hazelwood, Kim ^a  

^a University of Virginia   (United States)

Author keywords

dynamic binary optimization; embedded systems; runtime adaptation; virtualization software

Indexed keywords

APPLICATION PROGRAMS; COMPUTER AIDED DESIGN; EMBEDDED SOFTWARE; VIRTUAL REALITY; VIRTUALIZATION;

BINARY MODIFICATION; DYNAMIC BINARY OPTIMIZATIONS; GENERAL-PURPOSE COMPUTING; OPERATING ENVIRONMENT; PROCESS-LEVEL VIRTUALIZATION; RESOURCECONSTRAINED DEVICES; RUNTIME ADAPTATION; VIRTUALIZATION SOFTWARE;

EMBEDDED SYSTEMS;

EID: 80052653257     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024924     Document Type: Conference Paper

References (25)

1. J. Baiocchi, B. R. Childers, J. W. Davidson, J. D. Hiser, and J. Misurda. Fragment cache management for dynamic binary translators in embedded systems with scratchpad. In Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES '07, pages 75-84, Salzburg, Austria, 2007.
2. V. Bala, E. Duesterwald, and S. Banerjia. Dynamo: a transparent dynamic optimization system. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '00, pages 1-12, Vancouver, BC, Canada, June 2000.
3. D. Bruening and S. Amarasinghe. Maintaining consistency and bounding capacity of software code caches. In Proceedings of the 3rd Annual IEEE/ACM International Symposium on Code Generation and Optimization, CGO '05, pages 74-85, San Jose, CA, March 2005.
4. D. Bruening, T. Garnett, and S. Amarasinghe. An infrastructure for adaptive dynamic optimization. In Proceedings of the 1st Annual IEEE/ACM International Symposium on Code Generation and Optimization, CGO '03, pages 265-275, San Francisco, CA, March 2003.
5. A. Cohen and E. Rohou. Processor virtualization and split compilation for heterogeneous multicore embedded systems. In Proceedings of the 47th Design Automation Conference, DAC '10, pages 102-107, Anaheim, California, 2010. ACM.
6. D. Davis and K. Hazelwood. Improving region selection through loop completion. In Proceedings of the ASPLOS Workshop on Runtime Environments, Systems, Layering, and Virtualized Environments, RESoLVE '11, Newport Beach, CA, March 2011.
7. G. Desoli, N. Mateev, E. Duesterwald, P. Faraboschi, and J. A. Fisher. Deli: A new run-time control point. In Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, MICRO-35, pages 257-268, Istanbul, Turkey, 2002.
8. B. Dhanasekaran and K. Hazelwood. Improving indirect branch translation in dynamic binary translators. In Proceedings of the ASPLOS Workshop on Runtime Environments, Systems, Layering, and Virtualized Environments, RESoLVE '11, Newport Beach, CA, March 2011.
9. A. Guha, K. Hazelwood, and M. L. Soa. Balancing memory and performance through selective ushing of software code caches. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES '10, pages 1-10, Scottsdale, AZ, October 2010.
10. K. Hazelwood. Dynamic Binary Modi cation: Tools, Techniques, and Applications. Morgan & Claypool Publishers, March 2011.
11. K. Hazelwood and A. Klauser. A dynamic binary instrumentation engine for the arm architecture. In Proceedings of the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, CASES '06, pages 261-270, Seoul, Korea, October 2006.
12. K. Hazelwood and M. D. Smith. Managing bounded code caches in dynamic binary optimization systems. Transactions on Code Generation and Optimization, 3(3):263-294, September 2006.
13. D. J. Hiniker, K. Hazelwood, and M. D. Smith. Improving region selection in dynamic optimization systems. In Proceedings of the 38th Annual International Symposium on Microarchitecture, MICRO-38, pages 141-154, Barcelona, Spain, November 2005.
14. J. D. Hiser, D. Williams, A. Filipi, J. W. Davidson, and B. R. Childers. Evaluating fragment construction policies for sdt systems. In Proceedings of the 2nd International Conference on Virtual Execution Environments, VEE '06, pages 122-132, Ottawa, Ontario, Canada, 2006.
15. J. D. Hiser, D. Williams, W. Hu, J. W. Davidson, J. Mars, and B. R. Childers. Evaluating indirect branch handling mechanisms in software dynamic translation systems. In Proceedings of the 5th Annual IEEE/ACM International Symposium on Code Generation and Optimization, CGO '07, pages 61-73, San Jose, CA, March 2007.
16. V. Kiriansky, D. Bruening, and S. Amarasinghe. Secure execution via program shepherding. In Proceedings of the 11th USENIX Security Symposium, pages 191-206, San Francisco, CA, August 2002.
17. J. Lu, H. Chen, P.-C. Yew, and W. chung Hsu. Design and implementation of a lightweight dynamic optimization system. Journal of Instruction-Level Parallelism, 6(1):1-24, April 2004.
18. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '05, pages 190-200, Chicago, IL, June 2005.
19. R. W. Moore, J. A. Baiocchi, B. R. Childers, J. W. Davidson, and J. D. Hiser. Addressing the challenges of dbt for the arm architecture. In Proceedings of the ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES '09, pages 147-156, Dublin, Ireland, 2009.
20. N. Nethercote and J. Seward. Valgrind: a framework for heavyweight dynamic binary instrumentation. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '07, pages 89-100, San Diego, CA, June 2007.
21. K. Scott, N. Kumar, S. Velusamy, B. Childers, J. W. Davidson, and M. L. Soffa. Retargetable and reconfigurable software dynamic translation. In Proceedings of the 1st Annual IEEE/ACM International Symposium on Code Generation and Optimization, CGO '03, pages 36-47, San Francisco, CA, March 2003.
22. D. Williams, A. Sanyal, D. Upton, J. Mars, S. Ghosh, , and K. Hazelwood. A cross-layer approach to heterogeneity and reliability. In Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE '09, pages 88-97, Cambridge, MA, July 2009.
23. L. Zhang and C. Krintz. Adaptive code unloading for resource-constrained jvms. In Proceedings of the ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES '04, pages 155-164, Washington, DC, 2004.
24. L. Zhang and C. Krintz. Profile-driven code unloading for resource-constrained jvms. In Proceedings of the 3rd International Symposium on Principles and Practice of Programming in Java, PPPJ '04, pages 83-90, Las Vegas, Nevada, 2004.
25. S. Zhou, B. R. Childers, and M. L. Soffa. Planning for code buffer management in distributed virtual execution environments. In Proceedings of the 1st ACM/USENIX International Conference on Virtual Execution Environments, VEE '05, pages 100-109, Chicago, IL, 2005.