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Volumn 43, Issue 3, 2008, Pages 26-35

Accelerating two-dimensional page walks for virtualized systems

Author keywords

AMD; Hypervisor; Memory Management; Nested Paging; Page Walk Caching; TLB; Virtual Machine Monitor; Virtualization

Indexed keywords

COMPUTER HARDWARE; VIRTUAL REALITY; VIRTUALIZATION;

EID: 67650075303     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: 10.1145/1353536.1346286     Document Type: Article
Times cited : (57)

References (19)
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    • Intel virtualization technology: Hardware support for efficient processor virtualization
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    • Neiger, G.1
  • 8
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    • Nov
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    • Gum, P.H.1
  • 9
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    • TLBs, paging structure caches, and their invalidation. Intel Application Note, 317080-001, April 2007.
    • TLBs, paging structure caches, and their invalidation. Intel Application Note, 317080-001, April 2007.
  • 14
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    • Formal requirements for virtualizable third generation architectures
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    • (1974) Commun. ACM , vol.17 , Issue.7 , pp. 412-421
    • Popek, G.J.1    Goldberg, R.P.2
  • 18
    • 70350667009 scopus 로고    scopus 로고
    • VMmark: A scalable benchmark for virtualized systems
    • Technical report, VMWare, 2006
    • V. Makhija et al. VMmark: A scalable benchmark for virtualized systems. Technical report, VMWare, 2006.
    • Makhija, V.1
  • 19
    • 34548818600 scopus 로고    scopus 로고
    • Low-power, high-performance architecture of the PWRficient processor family
    • T.-Y. Yeh. Low-power, high-performance architecture of the PWRficient processor family. Hot Chips 18, 2006.
    • (2006) Hot Chips , vol.18
    • Yeh, T.-Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.