Reliability analysis of H-Tree random access memories implemented with built in current sensors and parity codes for multiple bit upset correction

IEEE Transactions on Reliability

Volumn 60, Issue 3, 2011, Pages 528-537

  Argyrides, Costas ^a   Chipana, Raul ^b   Vargas, Fabian ^b   Pradhan, Dhiraj K ^c  

^a CA Evolvit Ltd   (Cyprus)

^b PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^c UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

Bit upset correction; built in current sensors; Hamming code; parity codes; random access memory reliability; single event upset

Indexed keywords

BUILT-IN CURRENT SENSORS; HAMMING CODE; PARITY CODES; RANDOM ACCESS MEMORIES; SINGLE EVENT UPSETS;

ERROR DETECTION; FAULT DETECTION; PLANT EXTRACTS; RELIABILITY ANALYSIS; SENSORS;

STATIC RANDOM ACCESS STORAGE;

EID: 80052392920     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2011.2161131     Document Type: Article

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