Embedding current monitoring in H-tree RAM architecture for multiple SEU tolerance and reliability improvement

Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008

Volumn , Issue , 2008, Pages 155-160

  Argyrides, Costas ^a   Vargas, Fabian ^b   Moraes, Marlon ^b   Pradhan, Dhiraj K ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

^b PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

BUSES; DATA STORAGE EQUIPMENT; ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; ERROR CORRECTION; QUALITY ASSURANCE; RANDOM ACCESS STORAGE; RELIABILITY; STATIC RANDOM ACCESS STORAGE; URANIUM POWDER METALLURGY;

BUILT-IN CURRENT SENSOR; BUS MONITORING; CURRENT DISSIPATION; HAMMING CODES; MEMORY CELLS; ON-LINE TESTING; PARITY BIT; RELIABILITY IMPROVEMENT; SEU TOLERANCE; SINGLE-EVENT UPSET; SRAM MEMORIES;

RELIABILITY ANALYSIS;

EID: 52049113633     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2008.36     Document Type: Conference Paper

References (15)

1. Pickel, J. C.; Blandford, Jr.; J. T. "Cosmic Ray Induced Errors in MOS Memory Cells". IEEE Transactions on Nuclear Science, vol. NS-25, no 6, Dec. 1978.
2. Mitra, S.; Seifert, N.; Zhang, M.; Shi, Q.; Kim, K.S. "Robust system design with built-in soft-error resilience". Transactions on Computers. Vol. 38, Issue 2, Feb. 2005. pp. 43-52.
3. Nicolaidis, M. Time "Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies". IEEE VLSI Test Symp. 1999, pp. 86.
4. Vargas, F.; Nicolaidis, M. "SEU-tolerant SRAM design based on current monitoring" Twenty-Fourth International Symposium on Fault-Tolerant Computing, 1994. FTCS-24. Digest of Papers, 15-17 Jun. 1994. pp. 106-115.
5. th 2008).
6. Bertozzi, D.; Benini, L.; De Micheli, G.; "Error control schemes for on-chip communication links: the energy-reliability tradeoffs", IEEE TCAD, vol. 24, no. 6, 2005.
7. Itoh, K. "Trends in Low-Power RAM Circuit Technologies", IEEE Proc., vol. 83, pp524-543, Apr. 1995.
8. Bhattacharjee S., Pradhan D. K., "LPRAM A novel Low-Power High-Performance RAM design with testability and Scalability", IEEE Transactions on Computers, vol. 23, no. 5, 2004.
9. Nicolaidis, M.; Vargas, F.; Courtois, B. Design of Built-In Current Sensors for Concurrent Checking in Radiation Environments. IEEE Transactions on Nuclear Science, Dec. 1993.
10. van de Goor, A. J. Testing Semiconductor Memories, Theory and Practice. John Wiley & Sons Ltd. West Sussex, England, 1991.
11. Feltham, D. B. I.; Nigh, P. J.; Carley, L. R.; Maly, W. "Current Sensing for Built-In Testing of CMOS Circuits" Proc. International Conference on Computer Design - Cambridge, MA. USA, 1988.
12. Shen, T.; Daly, J.C.; Lo, J.C. On-Chip Current Sensing Circuit for CMOS VLSI. Proc. 10th IEEE VLSI Test Symposium - Apr. 1992.
13. Lo, J.C.; Daly, J.C.; Nicolaidis, M. "Design of static CMOS Self-Checking Circuits Using Built-In Current Sensing". Proc. of Int. Conference on Fault Tolerant Computing - Jun. 1992, Boston MA.
14. nd IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT'07), Sep. 2007.
15. th Annual Symp. on Integrated Circuits and System Design SBCCI '07, Sep. 2007.