A miniature Q-band CMOS LNA with quadruple-cascode topology

IEEE MTT-S International Microwave Symposium Digest

Volumn , Issue , 2011, Pages

  Yeh, Han Chih ^a   Wang, Huei ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

cascode; CMOS; Low noise amplifier; MMIC

Indexed keywords

CASCODE; CASCODE DEVICE; CHIP SIZES; CMOS; CMOS LNA; CMOS TECHNOLOGY; COMPACT CHIP; HIGH GAIN; LOW POWER; MINIMUM NOISE FIGURE; SMALL SIGNAL GAIN;

CMOS INTEGRATED CIRCUITS; NOISE FIGURE; TOPOLOGY;

LOW NOISE AMPLIFIERS;

EID: 80052340081     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSYM.2011.5972656     Document Type: Conference Paper

References (15)

1. Shih-Chieh Shin, et al., "A 3.9-dB NF low-noise amplifier using 0.18-μm CMOS technology," IEEE MWCL, vol. 15, no. 7, pp. 448-450, July 2005.
2. Antonio Liscidini, et al., "Common gate transformer feedback LNA in a high IIP3 current mode RF CMOS front-end," IEEE 2006 CICC Proc., Sep. 2006, pp. 25-28.
3. Jeng-Han Tsai, et al., "A miniature Q-band low noise amplifier using 0.13-μm CMOS technology," IEEE MWCL, vol. 16, no. 6, pp. 327-329, June 2006.
4. M.A. Masud, et al., "90 nm CMOS MMIC amplifier," in IEEE RFIC Symp. Dig., June 2004, pp. 201-204.
5. Kuo-Jung Sun, et al., "A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors,"IEEE T-MTT, vol. 54, no. 4, pp. 1554-1560, Apr. 2006.
6. H. Shigematsu, et al., "Millimeter-wave CMOS circuit design,"IEEE T-MTT, vol. 53, no. 2, pp. 472-477, Feb. 2005.
7. F. Ellinger, "26-42 GHz SOI CMOS low noise amplifier," IEEE JSSC, vol. 39, no. 3, pp. 522-528, Mar. 2004.
8. C. H. Doan, et al., "Millimeter-wave CMOS design," IEEE JSSC, vol. 40, no. 1, pp. 144-155, Jan. 2005.
9. Chieh-Min Lo, Chin-Shen Lin, and Huei Wang, "A miniature V-band 3-stage cascode LNA in 0.13?m CMOS," ISSCC Dig. Tech. papers, pp. 402-403, Feb. 2006.
10. Hyoung-Seok Oh, et al., "A watt-level stacked-FET linear power amplifier in silicon-on-insulator CMOS," IEEE T-MTT, vol. 10, no. 1, pp.57-64, Jan. 2010.
11. Kuo-Jung Sun, et al., "A 10.8-GHz CMOS low-noise amplifier using parallel-resonant inductor," IEEE MTT-S IMS, Dig., 2007, pp. 1795-1798.
12. M. Varonnen, et al., "Millimeter-wave integrated circuits in 65-nm CMOS," IEEE JSSC, vol. 43, no. 9, pp. 1991-2002, Sep.2008.
13. Bo-Jr Huang, et al., "Millimeter-wave low power and miniature CMOS multicascode low-noise amplifiers with noise Reduction topology," IEEE T-MTT, vol. 57, no. 12, pp.3049-3059, Dec 2009.
14. R. A. Pucel, H. A. Haus, and H. Statz, "Signal and noise properties of gallium arsenide field effect transistors," in Advances in Electronics and Electron Physics, L. Morton, Ed . New York: Academic, 1975, vol. 38, pp. 195-265.
15. A. Amer, E. Hegazi, and H. Ragai, "A Low-Power Wideband CMOS LNA for WiMAX", IEEE Tran. on Circuit and Systems-II: Express Briefs, vol.54, pp. 4-8, Jan. 2007. (Pubitemid 46357242)