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Volumn 80, Issue , 2011, Pages 812-818

Adaptive sampling algorithm for ANN-based performance modeling of nano-scale CMOS inverter

Author keywords

Adaptive Sampling; Artificial Neural Network; CMOS Inverter; Nano scale

Indexed keywords

ADAPTIVE SAMPLING; ADAPTIVE SAMPLING ALGORITHMS; ADAPTIVE TECHNIQUE; ARTIFICIAL NEURAL NETWORK; CMOS INVERTERS; NANO SCALE; NETWORK-BASED; PERFORMANCE MODEL; PERFORMANCE MODELING; PROGRESSIVE SAMPLING; SPICE SIMULATIONS; TRAINING DATA;

EID: 80052173168     PISSN: 2010376X     EISSN: 20103778     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (4)

References (22)
  • 1
    • 0000195442 scopus 로고    scopus 로고
    • Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits
    • December
    • Georges. G.E. Gielen and Rob. A. Rutenbar. Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits. Proceedings of the IEEE, Vol.88:pp.1825-1852, December 2000.
    • (2000) Proceedings of the IEEE , vol.88 , pp. 1825-1852
    • Georges, G.E.1    Gielen2    Rutenbar, R.A.3
  • 2
    • 46149125307 scopus 로고    scopus 로고
    • Automation in Mixed-Signal Design: Challenges and Solutions in the Wake of the Nano Era
    • In, November
    • T. McConaghy and G. Gielen. Automation in Mixed-Signal Design: Challenges and Solutions in the Wake of the Nano Era. In Proc. of ICCAD, pages 461-463, November 2006.
    • (2006) Proc. of ICCAD , pp. 461-463
    • McConaghy, T.1    Gielen, G.2
  • 3
    • 48949106187 scopus 로고    scopus 로고
    • Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs
    • March
    • Rob.A. Rutenbar, Georges.G.E. Gielen, and J. Roychowdhury. Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs. Proceedings of the IEEE, Vol.95:pp.640-669, March 2007.
    • (2007) Proceedings of the IEEE , vol.95 , pp. 640-669
    • Rutenbar, R.A.1    Georges, G.E.2    Roychowdhury, G.J.3
  • 4
    • 0037515539 scopus 로고    scopus 로고
    • Simulation-Based Generation of Posynomial Performance Models for the Sizing of Analog Integrated Circuits
    • May
    • W. Daems, G. Gielen, and W. Sansen. Simulation-Based Generation of Posynomial Performance Models for the Sizing of Analog Integrated Circuits. IEEE Trans. CADICS, Vol.22:pp.517-534, May 2003.
    • (2003) IEEE Trans. CADICS , vol.22 , pp. 517-534
    • Daems, W.1    Gielen, G.2    Sansen, W.3
  • 5
    • 33746634313 scopus 로고    scopus 로고
    • Neural Network Based MOS Transistor Geometry Decision for TSMC 0.18 Process Technology
    • In
    • M. Avci and T. Yildirim. Neural Network Based MOS Transistor Geometry Decision for TSMC 0.18 Process Technology. In Proc. of ICCS, pages 615-622, 2006.
    • (2006) Proc. of ICCS , pp. 615-622
    • Avci, M.1    Yildirim, T.2
  • 7
    • 51849090086 scopus 로고    scopus 로고
    • Technology Independent Circuit Sizing for Fundamental Analog Circuits using Artificial Neural Networks
    • In
    • N. Kahraman and T. Yildirim. Technology Independent Circuit Sizing for Fundamental Analog Circuits using Artificial Neural Networks. In Proc. of PRIME, pages 1-4, 2008.
    • (2008) Proc. of PRIME , pp. 1-4
    • Kahraman, N.1    Yildirim, T.2
  • 8
    • 67349086060 scopus 로고    scopus 로고
    • Technology independent circuit sizing for standard cell based design using neural network
    • N. Kahraman and T. Yildirim. Technology independent circuit sizing for standard cell based design using neural network. Digital Signal Processing, Vol.19:pp.708-714, 2009.
    • (2009) Digital Signal Processing , vol.19 , pp. 708-714
    • Kahraman, N.1    Yildirim, T.2
  • 9
    • 33846564341 scopus 로고    scopus 로고
    • An approach based on neural computation to simulate the nanoscale CMOS circuit
    • F. Djeffala, M. Chahdib, A. Benhayaa, and M.L. Hafianea. An approach based on neural computation to simulate the nanoscale CMOS circuit. Solid State Electronics, Vol.51:pp.48-56, 2007.
    • (2007) Solid State Electronics , vol.51 , pp. 48-56
    • Djeffala, F.1    Chahdib, M.2    Benhayaa, A.3    Hafianea, M.L.4
  • 10
    • 37249037028 scopus 로고    scopus 로고
    • ANN-and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs
    • January
    • S.K. Mandal, S. Sural, and A. Patra. ANN-and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs. IEEE Transaction CADICS, Vol.27:pp.188-192, January 2008.
    • (2008) IEEE Transaction CADICS , vol.27 , pp. 188-192
    • Mandal, S.K.1    Sural, S.2    Patra, A.3
  • 13
    • 0242698067 scopus 로고    scopus 로고
    • The Learning-Curve Sampling Method Applied to Model-Based Clustering
    • February
    • C. Meek, B. Thiesson, and D. Heckerman. The Learning-Curve Sampling Method Applied to Model-Based Clustering. Journal of Machine Learning Research, Vol.2:pp.397-418, February 2002.
    • (2002) Journal of Machine Learning Research , vol.2 , pp. 397-418
    • Meek, C.1    Thiesson, B.2    Heckerman, D.3
  • 14
    • 26944477389 scopus 로고    scopus 로고
    • A Dynamic Adaptive Sampling Algorithm for Real World Applications: Finger Print Recognition and Face Recognition
    • In
    • A. Satyanarayana and I. Davidson. A Dynamic Adaptive Sampling Algorithm for Real World Applications: Finger Print Recognition and Face Recognition. In Proc. of ISMIS, pages 631-640, 2005.
    • (2005) Proc. of ISMIS , pp. 631-640
    • Satyanarayana, A.1    Davidson, I.2
  • 15
  • 16
    • 16244389968 scopus 로고    scopus 로고
    • Adaptive Sampling and Modeling of Analog Circuit Performance Parameters with Pseudo-Cubic Splines
    • 931-836
    • G. Wolfe and R. Vemuri. Adaptive Sampling and Modeling of Analog Circuit Performance Parameters with Pseudo-Cubic Splines. In Proc. of ICCAD, pages 931-836, 2004.
    • (2004) Proc. of ICCAD
    • Wolfe, G.1    Vemuri, R.2
  • 17
    • 80052179463 scopus 로고    scopus 로고
    • Performance Modeling of Nano-scale CMOS Inverter using Artificial Neural Network
    • In
    • D. Dhabak and S. Pandit. Performance Modeling of Nano-scale CMOS Inverter using Artificial Neural Network. In Proc. of IESPC, pages 33-36, 2011.
    • (2011) Proc. of IESPC , pp. 33-36
    • Dhabak, D.1    Pandit, S.2
  • 18
    • 0242586049 scopus 로고    scopus 로고
    • Artificial Neural Networks for RF and Microwave Design: From Theory to Practice
    • April
    • Q.J. Zhang, K.C. Gupta, and V.K. Devabhaktuni. Artificial Neural Networks for RF and Microwave Design: From Theory to Practice. IEEE Trans. MTT, Vol.51:1339-1350, April 2003.
    • (2003) IEEE Trans. MTT , vol.51 , pp. 1339-1350
    • Zhang, Q.J.1    Gupta, K.C.2    Devabhaktuni, V.K.3
  • 19
    • 33750600861 scopus 로고    scopus 로고
    • New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration
    • November
    • W. Zhao and Y. Cao. New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration. IEEE Transactions Electron Devices, Vol.53:pp.2816-2823, November 2006.
    • (2006) IEEE Transactions Electron Devices , vol.53 , pp. 2816-2823
    • Zhao, W.1    Cao, Y.2
  • 21
    • 0032295215 scopus 로고    scopus 로고
    • Modeling of Strength of High-Performance Concrete using Artificial Neural Network
    • I. C. Yeh. Modeling of Strength of High-Performance Concrete using Artificial Neural Network. Cement and Concrete Research, Vol.28:pp.1797-1808, 1998.
    • (1998) Cement and Concrete Research , vol.28 , pp. 1797-1808
    • Yeh, I.C.1
  • 22
    • 84857628247 scopus 로고    scopus 로고
    • http://archive.ics.uci.edu/ml/datasets/Concrete+Compressive+Strength.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.