A hardware acceleration technique for gradient descent and conjugate gradient

Proceedings of the 2011 IEEE 9th Symposium on Application Specific Processors, SASP 2011

Volumn , Issue , 2011, Pages 94-101

  Kesler, David ^a   Deka, Biplab ^a   Kumar, Rakesh ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AS GRAPH; COMPUTATION TIME; CONJUGATE GRADIENT; CONJUGATE GRADIENT ALGORITHMS; GRADIENT DESCENT; HARDWARE ACCELERATION; HARDWARE ACCELERATORS; LEAST SQUARE; LINEAR ALGEBRA OPERATIONS; NON-ITERATIVE; NUMERICAL OPTIMIZATIONS; PERFORMANCE LOSS; PROCESSOR POWER; ROBUSTIFICATION; SOFTWARE SUPPORT; SPARSE MATRICES;

ALGORITHMS; LINEAR ALGEBRA; PATTERN MATCHING;

CONJUGATE GRADIENT METHOD;

EID: 79961187689     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SASP.2011.5941086     Document Type: Conference Paper

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