SHA-less pipelined ADC with in situ background clock-skew calibration

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 8, 2011, Pages 1893-1903

  Huang, Pingli ^a,b   Hsien, Szukang ^c   Lu, Victor ^d   Wan, Peiyuan ^e   Lee, Seung Chul ^a,b   Liu, Wenbo ^f   Chen, Bo Wei ^g   Lee, Yung Pin ^g   Chen, Wen Tsao ^g   Yang, Tzu Yi ^g   Ma, Gin Kou ^g   Chiu, Yun ^a  

^a UNIVERSITY OF TEXAS AT DALLAS   (United States)

^b United States of America   (United States)

^c TEXAS INSTRUMENTS   (United States)

^d University of Illinois at Urbana Champaign   (United States)

^e BEIJING UNIVERSITY OF TECHNOLOGY   (China)

^f BROADCOM CORPORATION   (United States)

^g INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Multibit pipeline architecture; pipelined analog to digital converter (ADC); sample and hold amplifier (SHA); sampling clock skew; SHA less; skew calibration

Indexed keywords

PIPELINE ARCHITECTURE; PIPELINED ANALOG-TO-DIGITAL CONVERTER; SAMPLE-AND-HOLD AMPLIFIER; SAMPLING CLOCKS; SHA-LESS; SKEW CALIBRATION;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CLOCKS; ERRORS; FREQUENCY CONVERTERS;

CALIBRATION;

EID: 79960841623     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2151510     Document Type: Conference Paper

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