Thermal modelling of 3D multicore systems in a flip-chip package

Proceedings - IEEE International SOC Conference, SOCC 2010

Volumn , Issue , 2010, Pages 379-383

  Vaddina, Kameswar Rao ^a,b   Mitra, Tamoghna ^c   Liljeberg, Pasi ^b   Plosila, Juha ^b  

^a TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

^b UNIVERSITY OF TURKU   (Finland)

^c ÅBO AKADEMI UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

3D SYSTEMS; 3D THERMAL MODEL; DESIGN FLEXIBILITY; DEVICE INTEGRATION; EXPERIMENTAL SIMULATIONS; FLIP-CHIP PACKAGES; HETEROGENEOUS INTEGRATION; HOT SPOT; INTERCONNECT POWER; MAXIMUM TEMPERATURE; MULTI-CORE SYSTEMS; OPERATING CONDITION; OPTIMAL PLACEMENT SOLUTIONS; SIGNAL DELAYS; SILICON DIE; THERMAL MODEL; THERMAL MODELLING; THERMAL PERFORMANCE; THREE-DIMENSIONAL (3D); TRANSIENT HEAT TRANSFER;

DIES; FLIP CHIP DEVICES; HEAT RESISTANCE; MIXED CONVECTION; PROGRAMMABLE LOGIC CONTROLLERS; THERMOGRAPHY (TEMPERATURE MEASUREMENT);

THREE DIMENSIONAL;

EID: 79960734708     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2010.5784700     Document Type: Conference Paper

References (9)

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